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path: root/drivers/gpu/drm/i915/i915_reg.h
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* drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaroundArun Siluvery2015-06-231-0/+2
* drm/i915: Reset request handling for gen8+Mika Kuoppala2015-06-181-0/+3
* drm/i915/bxt: eDP Panel Power sequencingVandana Kannan2015-06-181-0/+13
* drm/i915: print FBC compression status on debugfsPaulo Zanoni2015-06-151-0/+3
* drm/i915: Delete duplicate #defines added for DCxChandra Konduru2015-06-151-6/+0
* drm/i915: Send GCP infoframes for deep color HDMI sinksVille Syrjälä2015-06-151-0/+3
* drm/i915: Implement WaEnableHDMI8bpcBefore12bpc:snb, ivbVille Syrjälä2015-06-151-0/+1
* drm/i915/skl: Derive the max CDCLK from DFSMDamien Lespiau2015-06-121-0/+7
* drm/i915: BDW clock change supportVille Syrjälä2015-06-121-0/+2
* drm/i915: Add cdclk extraction for g33, g965gm and g4xVille Syrjälä2015-05-291-0/+3
* drm/i915: Fix i855 get_display_clock_speedVille Syrjälä2015-05-291-3/+8
* drm/i915: Throw out WIP CHV power well definitionsVille Syrjälä2015-05-281-4/+0
* drm/i915: Use the default 600ns LDO programming sequence delayVille Syrjälä2015-05-281-0/+4
* drm/i915: Enable GTT caching on gen8Ville Syrjälä2015-05-221-0/+2
* drm/i915: Clean up the CPT DP .get_hw_state() port readoutVille Syrjälä2015-05-211-0/+1
* drm/i915/skl: Deinit/init the display at suspend/resumeDamien Lespiau2015-05-211-0/+3
* drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+Imre Deak2015-05-211-0/+1
* drm/i915/bxt: Port PLL programming BUNVandana Kannan2015-05-201-0/+6
* drm/i915: Adding dbuf support for skl nv12 format.Chandra Konduru2015-05-201-0/+11
* drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHVVille Syrjälä2015-05-081-1/+4
* drm/i915: Implement chv display PHY lane stagger setupVille Syrjälä2015-05-081-0/+13
* drm/i915/skl: Fix WaDisableChickenBitTSGBarrierAckForFFSliceCSDamien Lespiau2015-05-081-1/+1
* drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharingNick Hoath2015-05-081-0/+1
* drm/i915/bxt: BLC implementationVandana Kannan2015-05-081-0/+12
* drm/i915: Merge the GEN9 memory latency PCU opcode with its friendsDamien Lespiau2015-05-081-6/+5
* drm/i915: Re-order the PCU opcodesDamien Lespiau2015-05-081-5/+5
* drm/i915/skl: Fix the CTRL typo in the DPLL_CRTL1 definesDamien Lespiau2015-05-081-9/+9
* drm/i915: Setup static bias for GPUDeepak S2015-05-081-0/+6
* drm/i915/skl: Implement enable/disable for Display C5 state.A.Sunil Kamath2015-05-081-0/+11
* Merge tag 'drm-intel-next-2015-04-23-fixed' of git://anongit.freedesktop.org/...Dave Airlie2015-05-081-32/+457
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| * drm/i915/bxt: VSwing programming sequenceVandana Kannan2015-04-161-0/+61
| * drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequenceSatheeshakrishna M2015-04-161-0/+76
| * drm/i915/bxt: Implement enable/disable for Display C9 stateA.Sunil Kamath2015-04-161-0/+5
| * drm/i915/bxt: add description about the BXT PHYsImre Deak2015-04-161-6/+12
| * drm/i915/bxt: add display initialize/uninitialize sequence (PHY)Vandana Kannan2015-04-161-0/+96
| * drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK)Vandana Kannan2015-04-161-0/+20
| * drm/i915: PSR: Remove wrong LINK_DISABLE.Rodrigo Vivi2015-04-141-1/+0
| * drm/i915/bxt: Enable GMBUS IRQShashank Sharma2015-04-141-0/+1
| * drm/i915/bxt: DDI Hotplug interrupt setupShashank Sharma2015-04-141-1/+22
| * drm/i915: add bxt gmbus supportJani Nikula2015-04-141-0/+3
| * Merge branch 'topic/bxt-stage1' into drm-intel-next-queuedDaniel Vetter2015-04-141-12/+14
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| | * drm/i915/bxt: add workaround to avoid PTE corruptionRobert Beckett2015-04-141-0/+1
| | * drm/i915/bxt: add WaDisableMaskBasedCammingInRCC workaroundBen Widawsky2015-04-141-0/+4
| | * drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaroundBen Widawsky2015-04-141-0/+1
| | * drm/i915/bxt: Support BXT in SSEU device status dumpJeff McGee2015-04-091-9/+4
| | * drm/i915/bxt: Determine BXT slice/subslice/EU infoJeff McGee2015-04-091-3/+1
| | * drm/i915/bxt: Add the plane4 related interrupt definitionsDamien Lespiau2015-04-091-0/+3
| * | drm/i915: Register definitions for skylake scalersChandra Konduru2015-04-131-0/+115
| * | drm/i915/skl: Support for 90/270 rotationSonika Jindal2015-04-101-0/+2
| * | drm/i915: Naming constants to be written to GEN9_PG_ENABLESagar Kamble2015-04-101-0/+2
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