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path: root/drivers/gpu/drm/i915/i915_irq.c
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* drm/i915: Split the ringbuffers from the rings (3/3)Oscar Mateo2014-05-221-1/+1
* drm/i915: Split the ringbuffers from the rings (2/3)Oscar Mateo2014-05-221-4/+4
* drm/i915: s/intel_ring_buffer/intel_engine_csOscar Mateo2014-05-221-14/+14
* drm/i915: Fix gen2 and hsw+ scanline counterVille Syrjälä2014-05-221-9/+5
* drm/i915: Draw a picture about video timingsVille Syrjälä2014-05-221-0/+50
* drm/i915: Improve gen3/4 frame counterVille Syrjälä2014-05-221-5/+16
* drm/i915: Add a small adjustment to the pixel counter on interlaced modesVille Syrjälä2014-05-221-0/+12
* drm/i915: Simplify the uncleared FIFO underrun detectionVille Syrjälä2014-05-221-11/+2
* drm/i915: Check for FIFO underruns at the end of modeset on gmchVille Syrjälä2014-05-221-0/+28
* drm/i915: Check for FIFO underuns when disabling reporting on gmch platformsVille Syrjälä2014-05-221-6/+12
* Merge branch 'topic/drm-vblank-rework' into drm-intel-next-queuedDaniel Vetter2014-05-211-2/+2
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| * drm/i915: Accurately initialize fifo underrun state on gmch platformsDaniel Vetter2014-05-211-2/+2
* | drm/i915/chv: Make CHV irq handler loop until all interrupts are consumedVille Syrjälä2014-05-201-15/+14
* | drrm/i915/chv: Use valleyview_pipestat_irq_handler() for CHVVille Syrjälä2014-05-201-73/+17
* | drm/i915/chv: Clarify VLV/CHV PIPESTAT bits a bit moreVille Syrjälä2014-05-201-2/+8
* | drm/i915: Convert uncleared FIFO underrun message to errorsVille Syrjälä2014-05-161-4/+4
* | drm/i915/bdw: Implement a basic PM interrupt handlerBen Widawsky2014-05-151-2/+72
* | drm/i915: Drop unecessary casts in i915_irq.cDaniel Vetter2014-05-121-6/+6
* | drm/i915/chv: Preliminary interrupt support for CherryviewVille Syrjälä2014-05-121-1/+224
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* drm/i915: Make sprite updates atomicVille Syrjälä2014-05-061-6/+19
* drm/i915: Move semaphore specific ring members to structBen Widawsky2014-05-051-2/+1
* drm/i915: Add intel_get_crtc_scanline()Ville Syrjälä2014-05-051-14/+42
* drm/i915: Fix scanout position for realVille Syrjälä2014-05-051-79/+23
* drm/i915: get a runtime PM ref for the deferred GPU reset workImre Deak2014-05-051-0/+10
* drm/i915: vlv: clear master interrupt flag when disabling interruptsImre Deak2014-05-051-0/+2
* drm/i915:Handle the irq interrupt for the second BSD ringZhao Yakui2014-05-051-1/+4
* Merge tag 'drm-intel-next-2014-04-16' of git://anongit.freedesktop.org/drm-in...Dave Airlie2014-05-011-272/+232
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| * drm/i915: Rename GEN8_PIPE_FLIP_DONE to PRIMARY_FLIP_DONEDamien Lespiau2014-04-091-2/+2
| * Merge remote-tracking branch 'airlied/drm-next' into HEADDaniel Vetter2014-04-091-2/+2
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| * | drm/i915: Provide a bit more info when pipestat bits are wrongVille Syrjälä2014-04-031-4/+8
| * | drm/i915: kill dev_priv->pm.regsavePaulo Zanoni2014-04-011-69/+10
| * | drm/i915: only enable HWSTAM interrupts on postinstall on ILK+Paulo Zanoni2014-04-011-6/+4
| * | drm/i915: add gen8_irq_resetPaulo Zanoni2014-04-011-19/+8
| * | drm/i915: add ironlake_irq_resetPaulo Zanoni2014-04-011-10/+11
| * | drm/i915: add missing intel_hpd_irq_uninstallPaulo Zanoni2014-04-011-0/+2
| * | drm/i915: remove ibx_irq_uninstallPaulo Zanoni2014-04-011-18/+5
| * | drm/i915: enable SDEIER laterPaulo Zanoni2014-04-011-6/+21
| * | drm/i915: call ibx_irq_uninstall from gen8_irq_uninstallPaulo Zanoni2014-04-011-0/+2
| * | drm/i915: extract ibx_irq_uninstallPaulo Zanoni2014-04-011-7/+14
| * | drm/i915: fix open coded gen5_gt_irq_preinstallPaulo Zanoni2014-04-011-6/+4
| * | drm/i915: fix GEN7_ERR_INT init/reset codePaulo Zanoni2014-04-011-3/+4
| * | drm/i915: fix SERR_INT init/reset codePaulo Zanoni2014-04-011-6/+7
| * | drm/i915: check if IIR is still zero at postinstall on Gen5+Paulo Zanoni2014-04-011-17/+20
| * | drm/i915: add GEN5_IRQ_INITPaulo Zanoni2014-04-011-18/+19
| * | drm/i915: properly clear IIR at irq_uninstall on Gen5+Paulo Zanoni2014-04-011-50/+27
| * | drm/i915: don't forget to uninstall the PM IRQsPaulo Zanoni2014-04-011-0/+2
| * | drm/i915: add GEN5_IRQ_FINIPaulo Zanoni2014-04-011-9/+9
| * | drm/i915: use GEN8_IRQ_INIT on GEN5Paulo Zanoni2014-04-011-27/+19
| * | drm/i915: also use GEN5_IRQ_INIT with south display interruptsPaulo Zanoni2014-04-011-2/+1
| * | drm/i915: add GEN5_IRQ_INIT macroPaulo Zanoni2014-04-011-14/+10
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