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| * | drm/amdgpu: move gtt usage tracking into the gtt manager v2Christian König2017-08-175-16/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It doesn't make much sense to count those numbers twice. v2: use and atomic64_t instead Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: move debug print into the MM managersChristian König2017-08-173-22/+11
| | | | | | | | | | | | | | | | | | | | | | | | Instead of the separate switch/case in the calling function. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix incorrect use of the lru_lockChristian König2017-08-171-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | The BO manager has its own lock and doesn't use the lru_lock. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/ttm: make ttm_mem_type_manager_func debug more usefulChristian König2017-08-172-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | Provide the drm printer directly instead of just the callback. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/amdgpu: Add tracepoint for DMA page mapping (v4)Tom St Denis2017-08-172-6/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This helps map DMA addresses back to physical addresses. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (v2): Added tracepoints for USERPTR, SG mappings, and SWIOTBL mappings. Reformatted trace call perform PCI decoding internal to the trace. (v3): Add unmap tracepoints as well (v4): Move traces into separate functions
| * | drm/amdgpu: fix Vega10 HW config for 2MB pagesChristian König2017-08-172-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Those values weren't correct. This should result in quite some speedup. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: only bind VM shadows after validation v2Christian König2017-08-171-14/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to do this on every CS. v2: remove all other bind, reorder code Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: only move VM BOs in the LRU during validation v2Christian König2017-08-173-59/+16
| |/ | | | | | | | | | | | | | | | | | | | | | | | | This should save us a bunch of command submission overhead. v2: move the LRU move to the right place to avoid the move for the root BO and handle the shadow BOs as well. This turned out to be a bug fix because the move needs to happen before the kmap. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * Merge branch 'drm-next-4.14' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2017-08-1846-1033/+574
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next More features for 4.14. Nothing too major here. I have a few more additional patches for large page support in vega10 among other things, but they require some resevation object patches from drm-misc-next, so I'll send that request once you've pulled the latest drm-misc-next. Highlights: - Fixes for ACP audio on stoney - SR-IOV fixes for vega10 - various powerplay fixes - lots of code clean up * 'drm-next-4.14' of git://people.freedesktop.org/~agd5f/linux: (62 commits) drm/amdgpu/gfx7: fix function name drm/amd/amdgpu: Disabling Power Gating for Stoney platform drm/amd/amdgpu: Added a quirk for Stoney platform drm/amdgpu: jt_size was wrongly counted twice drm/amdgpu: fix missing endian-safe guard drm/amdgpu: ignore digest_size when loading sdma fw for raven drm/amdgpu: Uninitialized variable in amdgpu_ttm_backend_bind() drm/amd/powerplay: fix coding style in hwmgr.c drm/amd/powerplay: refine dmesg info under powerplay. drm/amdgpu: don't finish the ring if not initialized drm/radeon: Fix preferred typo drm/amdgpu: Fix preferred typo drm/radeon: Fix stolen typo drm/amdgpu: Fix stolen typo drm/amd/powerplay: fix coccinelle warnings in vega10_hwmgr.c drm/amdgpu: set gfx_v9_0_ip_funcs as static drm/radeon: switch to drm_*{get,put} helpers drm/amdgpu: switch to drm_*{get,put} helpers drm/amd/powerplay: add CZ profile support drm/amd/powerplay: fix PSI not enabled by kmd ...
| | * drm/amdgpu/gfx7: fix function nameAlex Deucher2017-08-151-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Was using the wrong prefix (gmc rather than gfx). The function is related to the gfx hw, not gmc. This also makes it consistent with the naming in gfx8. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/amdgpu: Disabling Power Gating for Stoney platformVijendar Mukunda2017-08-151-23/+28
| | | | | | | | | | | | | | | | | | | | | | | | Power Gating is disabled in Stoney platform. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/amdgpu: Added a quirk for Stoney platformVijendar Mukunda2017-08-151-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added DW_I2S_QUIRK_16BIT_IDX_OVERRIDE quirk for Stoney. Supported format and bus width for I2S controller read from I2S Component Parameter registers. These are ready only registers. For Stoney, I2S Component Parameter registers are programmed to support 32 bit format and 4 bytes bus width only. By setting this quirk,It will override 32 bit format with 16 bit format and 2 bytes as bus width for Stoney. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: jt_size was wrongly counted twiceEvan Quan2017-08-151-2/+0
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: fix missing endian-safe guardEvan Quan2017-08-151-1/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: ignore digest_size when loading sdma fw for ravenHawking Zhang2017-08-151-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | digest_size has been retired from sdma v4 fw Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: Uninitialized variable in amdgpu_ttm_backend_bind()Dan Carpenter2017-08-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | My static checker complains that it's possible for "r" to be uninitialized. It used to be set to zero so this returns it to the old behavior. Fixes: 98a7f88ce9a9 ("drm/amdgpu: bind BOs with GTT space allocated directly v2") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: don't finish the ring if not initializedTrigger Huang2017-08-151-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a ring is not initialized, it also should not be finished. For example, in Vega10's SR-IOV environment, UVD's decode ring is not initialized, but will be finnished in amdgpu_uvd_sw_fini, because UVD driver put all the uvd decode ring's finish operation into amdgpu_uvd_sw_fini function, while not uvd_vXXX_0_sw_fini. This will lead to amdgpu module unloading failure. Signed-off-by: Trigger Huang <trigger.huang@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: Fix preferred typoKent Russell2017-08-157-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | Change "prefered" to "preferred" Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: Fix stolen typoKent Russell2017-08-152-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | Change "stollen" to "stolen" Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: set gfx_v9_0_ip_funcs as staticHuang Rui2017-08-152-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | We won't use this member in other files, so set it static. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: switch to drm_*{get,put} helpersCihangir Akturk2017-08-159-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drm_*_reference() and drm_*_unreference() functions are just compatibility alias for drm_*_get() and drm_*_put() and should not be used by new code. So convert all users of compatibility functions to use the new APIs. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Cihangir Akturk <cakturk@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: use 256 bit buffers for all wb allocations (v2)Alex Deucher2017-08-153-126/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | May waste a bit of memory, but simplifies the interface significantly. v2: convert internal accounting to use 256bit slots Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: Make amdgpu_atif_handler staticJean Delvare2017-08-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are no external users of function amdgpu_atif_handler so it can be static. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: Fix amdgpu_pm_acpi_event_handler warningJean Delvare2017-08-152-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Include a missing header to get rid of the following warning: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:65:6: warning: no previous prototype for ‘amdgpu_pm_acpi_event_handler’ [-Wmissing-prototypes] void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) ^ Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: Fix dce_v6_0_disable_dce warningJean Delvare2017-08-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Include a missing header to get rid of the following warning: drivers/gpu/drm/amd/amdgpu/dce_v6_0.c:521:6: warning: no previous prototype for 'dce_v6_0_disable_dce' [-Wmissing-prototypes] void dce_v6_0_disable_dce(struct amdgpu_device *adev) ^ Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: Fix undue fallthroughs in golden registers initializationJean Delvare2017-08-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As I was staring at the si_init_golden_registers code, I noticed that the Pitcairn initialization silently falls through the Cape Verde initialization, and the Oland initialization falls through the Hainan initialization. However there is no comment stating that this is intentional, and the radeon driver doesn't have any such fallthrough, so I suspect this is not supposed to happen. Signed-off-by: Jean Delvare <jdelvare@suse.de> Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10") Cc: Ken Wang <Qingqing.Wang@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Marek Olšák" <maraeo@gmail.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| | * drm/amdgpu/sdma4: move wptr polling setupAlex Deucher2017-08-151-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move it up before ring enablement with all of the other engine setup and explicitly disable it for bare metal. Cc: Frank Min <Frank.Min@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/sdma4: drop allocation of poll_mem_offsAlex Deucher2017-08-152-37/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | We already allocate this as part of the ring structure, use that instead. Cc: Frank Min <Frank.Min@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/sdma4: drop hdp flush from wptr shadow updateAlex Deucher2017-08-151-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The wb buffer is in system memory, not vram so the flush is useless. Cc: Frank Min <Frank.Min@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/sdma4: set wptr shadow atomically (v2)Alex Deucher2017-08-151-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No functional change until wptr polling uses this location (future patch). v2: use WRITE_ONCE Cc: Frank Min <Frank.Min@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: Fix KFD initialization for multi-GPU systemsFelix Kuehling2017-08-153-22/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kfd2kgd is device-specific, so it should not be a global variable. Merge amdgpu_amdkfd_load_interface and amdgpu_amdkfd_device_probe so that it's only needed as a local variable in one function. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/sdma4: drop unused register headerAlex Deucher2017-08-151-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | nbio registers are not used in this file. Reviewed-by: Christian König <christian.koenig@amd.com> Cc: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: drop old ip definitions for gfxhub and mmhubAlex Deucher2017-08-152-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gfxhub and mmhub code are now helpers for gmc rather than standalone IPs. When that changes these were left over. Remove them. Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: make wb 256bit function names consistentAlex Deucher2017-08-153-3/+3
| | | | | | | | | | | | | | | | | | | | | Use a lower case b to be consistent with the other wb functions. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: Support IOMMU on RavenYong Zhao2017-08-152-5/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We achieved that by setting S(SYSTEM) and P(PDE as PTE) bit to 1 for PDEs and setting S bit to 1 for PTEs when the corresponding addresses are not occupied by gpu driver allocated buffers. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: Add a parameter to amdgpu_bo_create()Yong Zhao2017-08-1514-20/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | The parameter init_value contains the value to which we initialized VRAM bo when AMDGPU_GEM_CREATE_VRAM_CLEARED flag is set. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: use amdgpu_bo_free_kernel more oftenChristian König2017-08-155-163/+15
| | | | | | | | | | | | | | | | | | | | | | | | Saves us even more loc. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: use amdgpu_bo_create_kernel more oftenChristian König2017-08-156-396/+103
| | | | | | | | | | | | | | | | | | | | | | | | Saves us quite a bunch of loc. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: add amdgpu_bo_create_reservedChristian König2017-08-152-8/+44
| | | | | | | | | | | | | | | | | | | | | | | | Same as amdgpu_bo_create_kernel, but keeps the BO reserved. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: improve amdgpu_bo_create_kernelChristian König2017-08-151-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | Make allocating the new BO optional. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: shadow and mn list are mutually exclusiveChristian König2017-08-151-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | Save some memory because only one of those is used at all times. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: move some defines aroundChristian König2017-08-152-68/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move amdgpu_bo and related structures into amdgpu_object.h. Move amdgpu_bo_list structures to the amdgpu_bo_list functions. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: consistent use u64_to_user_ptrChristian König2017-08-153-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Instead of open coding the conversion from u64 to pointers. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: cleanup kptr handlingChristian König2017-08-155-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | Don't keep around the same pointer twice. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: update vega10 golden settingEvan Quan2017-08-151-0/+2
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Ken Wang <ken.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/sdma4: Enable sdma poll mem addr on vega10 for SRIOVFrank Min2017-08-152-3/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While doing flr on VFs, there is possibility to lost the doorbell writing for sdma, so enable poll mem for sdma, then sdma fw would check the pollmem holding wptr. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/uvd7: optimize uvd initialization sequence for SRIOVFrank Min2017-08-151-47/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1.Since in sriov there is no need of decoding, so skip the related code; 2.Vcpu boot up and umc enable need to take at the end of the init sequence; Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/vce4: optimize vce 4.0 init table sequence for SRIOVFrank Min2017-08-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Optimize init table sequence for sriov. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: According hardware design revert vce and uvd doorbell assignmentFrank Min2017-08-153-15/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now uvd doorbell is from 0xf8-0xfb and vce doorbell is from 0xfc-0xff Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: Skip uvd and vce ring test for SRIOVFrank Min2017-08-152-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since rptr would not be accessed on later secure asics in sriov, remove the ring test. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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