summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
Commit message (Collapse)AuthorAgeFilesLines
* drm/amdgpu: Add CLK IP base offsetRex Zhu2018-07-101-0/+1
| | | | | | | | | so we can read/write the registers in CLK domain through RREG32/WREG32_SOC15 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add MP1 and THM hw ip base reg offsetEvan Quan2018-04-111-1/+2
| | | | | | Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: include new ip and ip offset headersHawking Zhang2018-02-191-1/+2
| | | | | | Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Dynamic initialize IP base offsetShaoyun Liu2017-12-081-0/+56
The base offsets of the IP blocks may change across asics even though the relative register offsets are the same for an IP. Handle this dynamically. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
OpenPOWER on IntegriCloud