summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu/soc15_common.h
Commit message (Collapse)AuthorAgeFilesLines
* drm/amdgpu: Add SOC15_WAIT_ON_RREG macro defineRex Zhu2018-05-241-0/+15
| | | | | | | | | Add new macro to wait on a register field to be a specific value. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: convert nbio to use callbacks (v2)Alex Deucher2017-12-131-16/+0
| | | | | | | | | Cleans up and consolidates all of the per-asic logic. v2: squash in "drm/amdgpu: fix NULL err for sriov detect" (Chunming) Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Change SOC15_REG_OFFSET to use dynamic register offsetShaoyun Liu2017-12-081-5/+1
| | | | | | Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const arrayShaoyun Liu2017-12-081-6/+0
| | | | | | | | Handle dynamic offsets correctly in static arrays. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Use dynamic IP offset for register access on SOC15Shaoyun Liu2017-12-081-26/+8
| | | | | | | | | Update the register access macros and functions to take into account the new dynamic IP base offsets. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add WREG32_SOC15_NO_KIQ macro defineShaoyun Liu2017-07-141-0/+7
| | | | | | Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/amdgpu: Add offset variant to SOC15 macrosTom St Denis2017-06-151-0/+14
| | | | | | | | | Allows reading/writing via SOC15 macros with offset for various register banks. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/amdgpu: Introduce new read/write macros for SOC15Tom St Denis2017-04-281-1/+19
| | | | | | Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add common soc15 headersKen Wang2017-03-291-0/+57
These are used by various IP modules. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
OpenPOWER on IntegriCloud