| Commit message (Collapse) | Author | Age | Files | Lines |
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pinctrl update from Linus Walleij:
"These are the pinctrl changes for v3.10:
- Patrice Chotard contributed a new configuration debugfs interface
and reintroduced fine-grained locking into the core: instead of
having a "big pinctrl lock" we have a per-controller lock and
specialized locks for the global controller and pinctrl handle
lists.
- Haoijan Zhuang deleted all the PXA and MMP2 pinctrl drivers and
replaced them with pinctrl-single (which is also used by other
SoCs) so we are gaining consolidation. The platform particulars
now come in through the device tree.
- Haoijan also added support for generic pin config into the
pinctrl-single driver which is another big consolidation win.
- Finally also GPIO ranges are now supported by the pinctrl-single
driver.
- Tomasz Figa contributed a new Samsung S3C pinctrl driver, bringing
more of the older Samsung platforms under the pinctrl umbrella and
out of arch/arm.
- Maxime Ripard contributed new Allwinner A10/A13 drivers.
- Sachin Kamat, Wei Yongjun and Axel Lin did a lot of cleanups."
* tag 'pinctrl-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (66 commits)
pinctrl: move subsystem mutex to pinctrl_dev struct
pinctrl/pinconfig: fix misplaced goto
pinctrl: s3c64xx: Fix build error caused by undefined chained_irq_enter
pinctrl/pinconfig: add debug interface
pinctrl: abx500: fix issue when no pdata
pinctrl: pinctrl-single: add missing double quote
pinctrl: sunxi: Rename wemac functions to emac
pinctrl: exynos5440: add gpio interrupt support
pinctrl: exynos5440: fix probe failure due to missing pin-list in config nodes
pinctrl: ab8505: Staticize some symbols
pinctrl: ab8540: Staticize some symbols
pinctrl: ab9540: Staticize some symbols
pinctrl: ab8500: Staticize some symbols
pinctrl: abx500: Staticize some symbols
pinctrl: Add pinctrl-s3c64xx driver
pinctrl: samsung: Handle banks with two configuration registers
pinctrl: samsung: Remove hardcoded register offsets
pinctrl: samsung: Split pin bank description into two structures
pinctrl: samsung: Include pinctrl-exynos driver data conditionally
pinctrl: samsung: Protect bank registers with a spinlock
...
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Linux 3.9-rc5
Conflicts:
drivers/pinctrl/pinconf.c
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commit 39b70ee051 "gpio: pl061: bind pinctrl by gpio request"
adds pl061_gpio_request() to request pinctrl.
Thus we need to add corresponding pl061_gpio_free() to free the pin.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add the pl061_gpio_request() to request pinctrl. Create the logic
between pl061 gpio driver and pinctrl (pinctrl-single) driver.
While a gpio pin is requested, it will request pinctrl driver to
set that pin with gpio function mode. So pinctrl driver should
append .gpio_request_enable() in pinmux_ops.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Drop the support of irq generic chip. Now support irqdomain instead.
Although set_wake() is defined in irq generic chip & it is not really
used in pl061 gpio driver. Drop it at the same time.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add gpio offset into "gpio-range-cells" property. It's used to support
sparse pinctrl range in gpio chip.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This reverts commit 6c7e660a27da7494c670bfba21cfeba30457656c.
The commit causes breakage on several older PXA machines.
Reported-by: Mike Dunn <mikedunn@newsguy.com>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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We actually have to pass chip as the host_data parameter of
irq_domain_add_simple() as later on, it is used to initialize chip_data
in pca953x_gpio_irq_map(). Failing to do so is leading to a NULL pointer
dereference after calling irq_data_get_irq_chip_data() in
pca953x_irq_mask(), pca953x_irq_unmask(), pca953x_irq_bus_lock(),
pca953x_irq_bus_sync_unlock() and pca953x_irq_set_type().
Fixes regression introduced by commit
0e8f2fdacf1d44651aa7e57063c76142d1f4988b (gpio: pca953x: use simple
irqdomain)
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO fixes from Linus Walleij:
"Two GPIO fixes for the v3.9 series:
- Fix erroneous return value in the ICH driver
- Make the STMPE driver proper properly on device tree boots"
* tag 'gpio-fixes-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio:
gpio: stmpe: pass DT node to irqdomain
gpio-ich: Fix value returned by ichx_gpio_request
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The irq domain was implemented but the device tree
node was not transmitted to irq_domain_add_simple().
Cc: stable@vger.kernel.org
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Per Documentation/gpio.txt, gpio_request callbacks should return 0 on
success or a negative value on error. So it is not clear what was
meant by letting ichx_gpio_request return 1 in some cases, nor how a
caller would interpret it.
Align the code with the comment above it and consider pins as
available by default.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pinctrl fixes from Linus Walleij:
"Here are a few pinctrl fixes for the v3.9 rc series:
- Usecount bounds checking so we do not go below zero on mux
usecounts.
- Loop range checking in GPIO ranges in the DT range parser.
- Proper print in debugfs for pinconf state.
- Fix compilation bug in generic pinconf code.
- Minor bugfixes to abx500 and mvebu drivers."
* tag 'pinctrl-fixes-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinmux: forbid mux_usecount to be set at UINT_MAX
pinctrl: mvebu: fix checking for SoC specific controls
pinctrl: generic: Fix compilation error
pinctrl: Print the correct information in debugfs pinconf-state file
pinctrl: abx500: Fix checking if pin use AlternateFunction register
gpio: fix wrong checking condition for gpio range
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If index++ calculates from 0, the checking condition of "while
(index++)" fails & it doesn't check any more. It doesn't follow
the loop that used at here.
Replace it by endless loop at here. Then it keeps parsing
"gpio-ranges" property until it ends.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Pull ARM SoC fixes from Arnd Bergmann:
"These bug fixes are for the largest part for mvebu/kirkwood, which saw
a few regressions after the clock infrastructure was enabled, and for
OMAP, which showed a few more preexisting bugs with the new
multiplatform support.
Other small fixes are for imx, mxs, tegra, spear and socfpga"
* tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits)
ARM: spear3xx: Use correct pl080 header file
Arm: socfpga: pl330: Add #dma-cells for generic dma binding support
ARM: multiplatform: Sort the max gpio numbers.
ARM: imx: fix typo "DEBUG_IMX50_IMX53_UART"
ARM: imx: pll1_sys should be an initial on clk
arm: mach-orion5x: fix typo in compatible string of a .dts file
arm: mvebu: fix address-cells in mpic DT node
arm: plat-orion: fix address decoding when > 4GB is used
arm: mvebu: Reduce reg-io-width with UARTs
ARM: Dove: add RTC device node
arm: mvebu: enable the USB ports on Armada 370 Reference Design board
ARM: dove: drop "select COMMON_CLK_DOVE"
rtc: rtc-mv: Add support for clk to avoid lockups
gpio: mvebu: Add clk support to prevent lockup
ARM: kirkwood: fix to retain gbe MAC addresses for DT kernels
ARM: kirkwood: of_serial: fix clock gating by removing clock-frequency
ARM: mxs: cfa10049: Fix fb initialisation function
ARM: SPEAr13xx: Fix typo "ARCH_HAVE_CPUFREQ"
ARM: OMAP: RX-51: add missing USB phy binding
clk: Tegra: Remove duplicate smp_twd clock
...
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The kirkwood SoC GPIO cores use the runit clock. Add code to
clk_prepare_enable() runit, otherwise there is a danger of locking up
the SoC by accessing the GPIO registers when runit clock is not
ticking.
Reported-by: Simon Baatz <gmbnomis@gmail.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Simon Baatz <gmbnomis@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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ichx_gpio_check_available() returns either 0 or -ENXIO depending on whether
the given GPIO is available or not. However, callers of this function treat
the return value as boolean:
...
if (!ichx_gpio_check_available(gpio, nr))
return -ENXIO;
which erroneusly fails when the GPIO is available and not vice versa.
Fix this by making the function return boolean as expected by the callers.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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This comment applies to gpio_to_chip(), not gpiod_to_chip().
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Constify descriptor parameter of gpiod_* functions for those that
should obviously not modify it. This includes value or direction get,
cansleep, and IRQ number query.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Some functions dereferenced their GPIO descriptor argument without
checking its validity first, potentially leading to an oops when given
an invalid argument.
This patch also makes gpio_get_value() more resilient when given an
invalid GPIO, returning 0 instead of silently crashing.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Cc: Ryan Mallon <rmallon@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Convert to the much saner new idr interface.
Signed-off-by: Tejun Heo <tj@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Pull GPIO changes from Grant Likely:
"This branch contains the usual set of individual driver improvements
and bug fixes, as well as updates to the core code. The more notable
changes include:
- Internally add new API for referencing GPIOs by gpio_desc instead
of number. Eventually this will become a public API
- ACPI GPIO binding support"
* tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux: (33 commits)
arm64: select ARCH_WANT_OPTIONAL_GPIOLIB
gpio: em: Use irq_domain_add_simple() to fix runtime error
gpio: using common order: let 'static const' instead of 'const static'
gpio/vt8500: memory cleanup missing
gpiolib: Fix locking on gpio debugfs files
gpiolib: let gpio_chip reference its descriptors
gpiolib: use descriptors internally
gpiolib: use gpio_chips list in gpiochip_find_base
gpiolib: use gpio_chips list in sysfs ops
gpiolib: use gpio_chips list in gpiochip_find
gpiolib: use gpio_chips list in gpiolib_sysfs_init
gpiolib: link all gpio_chips using a list
gpio/langwell: cleanup driver
gpio/langwell: Add Cloverview ids to pci device table
gpio/lynxpoint: add chipset gpio driver.
gpiolib: add missing braces in gpio_direction_show
gpiolib-acpi: Fix error checks in interrupt requesting
gpio: mpc8xxx: don't set IRQ_TYPE_NONE when creating irq mapping
gpiolib: remove gpiochip_reserve()
arm: pxa: tosa: do not use gpiochip_reserve()
...
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Adjust the gpio-em.c driver to reconsider the pdata->irq_base
variable. Non-DT board code like for instance board-kzm9d.c
needs to operate of a static IRQ range for platform devices.
So this patch is updating the code to make use of the function
irq_domain_add_simple() instead of irq_domain_add_linear().
Fixes a EMEV2 / KZM9D runtime error caused by the following commit:
7385500 gpio/em: convert to linear IRQ domain
Cc: stable@kernel.org
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Reported-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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'const static ' is not a common order, better to use 'static const' instead.
building:
make EXTRA_CFLAGS=-W ARCH=arm
drivers/gpio/gpio-omap.c:1479:
warning: 'static' is not at beginning of declaration
drivers/gpio/gpio-omap.c:1485:
warning: 'static' is not at beginning of declaration
drivers/gpio/gpio-omap.c:1491:
warning: 'static' is not at beginning of declaration
Signed-off-by: Chen Gang <gang.chen@asianux.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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This driver is missing a .remove callback, and the fail path on
probe is incomplete.
If an error occurs in vt8500_add_chips, gpio_base is not unmapped.
The driver is also ignoring the return value from this function so
if a chip fails to register it completes as successful.
Replaced pr_err with dev_err in vt8500_add_chips since the device is
available.
There is also no .remove callback defined so the function is added.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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The debugfs files really need to hold the gpiolib spinlock before
accessing the list. Otherwise chip addition/removal will cause an oops.
Cc: Alexandre Courbot <acourbot@nvidia.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Add a pointer to the gpio_chip structure that references the array of
GPIO descriptors belonging to the chip, and update gpiolib code to use
this pointer instead of the global gpio_desc[] array. This is another
step towards the removal of the gpio_desc[] global array.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.orh>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Make sure gpiolib works internally with descriptors and (chip, offset)
pairs instead of using the global integer namespace. This prepares the
ground for the removal of the global gpio_desc[] array and the
introduction of the descriptor-based GPIO API.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
[grant.likely: Squash in fix for link error when CONFIG_SYSFS=n]
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Re-implement gpiochip_find_base using the list of chips instead of the
global gpio_desc[] array. This makes it both simpler and more efficient,
and is needed to remove the global descriptors array.
The new code should preserve the exact same GPIO number assignment
policy as the code it is replacing. There shouldn't be any visible
change to the assigned GPIO numbers.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
[grant.likely: Added comment about assignment policy]
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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This makes the code both simpler and faster compared to parsing the GPIO
number space.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Using the GPIO chips list is much faster than parsing the entire GPIO
number space.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Use the small list of GPIO chips instead of parsing the whole GPIO
number space.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Add a list member to gpio_chip that allows all chips to be parsed
quickly. The current method requires parsing the entire GPIO integer
space, which is painfully slow. Using a list makes many chip operations
that involve lookup or parsing faster, and also simplifies the code. It
is also necessary to eventually get rid of the global gpio_desc[] array.
The list of gpio_chips is always ordered by base GPIO number to ensure
chips traversal is done in the right order.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git into gpio/next
Device driver features, cleanups and bug fixes.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Add missing braces in an if..else condition.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Print error message if requesting an interrupt fails.
Use int instead of unsigned for interrupts in case of error values
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Exporting gpios over sysfs GPIO interface throws genirq
error messages, i.e. on an mpc5121 based board exporting
GPIO 5 triggers it:
# echo 229 > /sys/class/gpio/export
genirq: Setting trigger mode 0 for irq 44 failed
(mpc512x_irq_set_type+0x0/0x18c)
Similar error messages appear in the kernel boot log since the
board specifies GPIOs for matrix keypad and also SD Card write
protect and card detect GPIOs in its device tree. For all these
GPIOs there is an error message in the log.
The issue is triggered by setting the irq type to IRQ_TYPE_NONE
in the driver's irq_domain map function mpc8xxx_gpio_irq_map().
...
mpc8xxx_gpio_irq_map
irq_set_irq_type
__irq_set_trigger
__irq_set_trigger() calls irq_set_type() callback of the mpc8xxx gpio
irq chip with the IRQ_TYPE_NONE in its 'flags' argument. This callback
is either mpc8xxx_irq_set_type() or mpc512x_irq_set_type(). Both these
functions return -EINVAL in the case if IRQ_TYPE_NONE is passed in the
flow_type argument. This return value triggers the observed error
message in __irq_set_trigger(). Modifying these callbacks to not
return an error in IRQ_TYPE_NONE case doesn't make any sense to me.
The line setting IRQ_TYPE_NONE type has been originally added by
commit 345e5c8a "powerpc: Add interrupt support to mpc8xxx_gpio".
At this time set_irq_type() checked its type argument and returned 0
if the type argument didn't specify any meaningful type in its type
sense bits (and thus was equal to IRQ_TYPE_NONE). Effectively this
line was a nop and I wonder what was the point of adding it.
Remove IRQ_TYPE_NONE setting in the irq_domain mapping function.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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gpiochip_reserve() has no user and stands in the way of the removal of
the static gpio_desc[] array. Remove this function as well as the now
unneeded RESERVED flag of struct gpio_desc.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This patch adds support for IRQ_TYPE_EDGE_BOTH needed for some driver
(gpio-keys).
Inspired from gpio-mxc.c
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add ability to handle ACPI events signalled by GPIO interrupts.
ACPI5 platforms can use GPIO signaled ACPI events. These GPIO interrupts are
handled by ACPI event methods which need to be called from the GPIO
controller's interrupt handler. acpi_gpio_request_interrupt() finds out which
gpio pins have acpi event methods and assigns interrupt handlers that calls
the acpi event methods for those pins.
Partially based on work by Rui Zhang <rui.zhang@intel.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Using the devm_* managed resources the pca driver can be simplified
and cut down on boilerplate code.
[gcl: fixed a inccorect reference to a removed label, "goto fail_out"
became "return ret"]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This switches the legacy irqdomain to the simple one, which will
auto-allocate descriptors, and also make sure that we use
irq_create_mapping() in the to_irq function. Also use the map function
of irq_domain_ops to setup the irq configuration on demand and no more
statically during the initialization of the driver.
Based on a initial patch from Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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gpio & pinctrl driver are used together. The pinctrl driver is already
launched before gpio driver in Makefile. So set gpio driver to module
init level. Otherwise, the sequence will be inverted.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Now that pca953x driver can handle GPIO expanders with more than 32
bits this patch adds the support for the pca9505 which cam with 40
GPIOs.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Until now the pca953x driver accessed all the bank of a given register
in a single command using only a 32 bits variable. New expanders from
the pca53x family come with 40 GPIOs which no more fit in a 32
variable. This patch make access to the registers more generic by
relying on an array of u8 variables. This fits exactly the way the
registers are represented in the hardware.
It also adds helpers to access to a single register of a bank instead
of reading or writing all the banks for a given register.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Replace subsys initcall by module initcall level. Since pinctrl
driver is already launched before gpio driver. It's unnecessary
to set gpio driver in subsys init call level.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Tested-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Some architectures (e.g. blackfin) provide gpio API without requiring
GPIOLIB support (ARCH_WANT_OPTIONAL_GPIOLIB). devm_gpio_* functions
should also work for these architectures, since they do not really
depend on GPIOLIB.
Add a new option GPIO_DEVRES (enabled by default) to control the build
of devres.c. It also removes the empty version of devm_gpio_*
functions for !GENERIC_GPIO build from linux/gpio.h, and moves the
function declarations from asm-generic/gpio.h into linux/gpio.h.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Use more coherent locking in the driver. Use bitfield to store the GPIO
direction and if the pin is configured as output store the status also in a
bitfiled.
In this way we can just look at these bitfields when we need information
about the pin status and only reach out to the chip when it is needed.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Move most of the global variables inside a private structure and allocate
it dynamically.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The vendor does not provide numbering for gpio pins. Vendor source
exports dedicated gpio pins first, followed by multifunction pins.
As this is what end users expect, this patch changes vt8500 and wm8505
to do the same.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This patch cleans up cosmetic issues, remove useless functions and add
to_lnw_priv() macro to replace many usages of container_of().
Signed-off-by: David Cohen <david.a.cohen@intel.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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