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* fpga: zynq-fpga: Fix issue with drvdata being overwritten.Moritz Fischer2015-10-231-3/+4
| | | | | | | | | | | | Upon registering a FPGA Manager low level driver, FPGA Manager core overwrites the platform drvdata pointer. Prior to this commit zynq-fpga falsely relied on this pointer to still be valid at remove() time. Reported-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Acked-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* fpga: zynq-fpga: Change fw format to handle bin instead of bit.Moritz Fischer2015-10-231-22/+2
| | | | | | | | | | This gets rid of the code to strip away the header and byteswap, as well as the check for the sync word. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-by: Josh Cartwright <joshc@ni.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* fpga: zynq-fpga: Fix unbalanced clock handlingMoritz Fischer2015-10-231-2/+2
| | | | | | | | | This commit fixes the unbalanced clock handling, where a failed probe would leave the clock with an enable count of -1. Reported-by: Josh Cartwright <joshc@ni.com> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000Moritz Fischer2015-10-171-0/+533
This commit adds FPGA Manager support for the Xilinx Zynq chip. The code borrows some from the xdevcfg driver in Xilinx' vendor tree. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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