summaryrefslogtreecommitdiffstats
path: root/drivers/edac/i7core_edac.c
Commit message (Collapse)AuthorAgeFilesLines
...
* i7core_edac: Fix ringbuffer maxsizeMauro Carvalho Chehab2010-05-101-6/+6
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: First store, then incrementMauro Carvalho Chehab2010-05-101-7/+6
| | | | | | | | | Fix ringbuffer store logic. While here, add a few comments to the code and remove the undesired printk that could otherwise be called during NMI time. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Better parse "any" addrmaskMauro Carvalho Chehab2010-05-101-1/+1
| | | | | | Instead of accepting just "any", accept also "any\n" Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Use a lockless ringbufferMauro Carvalho Chehab2010-05-101-28/+55
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Convert UDIMM error counters into a proper sysfs groupMauro Carvalho Chehab2010-05-101-37/+44
| | | | | | | | | | | | | | | | | Instead of displaying 3 values at the same var, break it into 3 different sysfs nodes: /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm0 /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm1 /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm2 For registered dimms, however, the error counters are already being displayed at: /sys/devices/system/edac/mc/mc0/csrow*/ce_count So, there's no need to add any extra sysfs nodes. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* edac: store/show methods for device groups weren't workingMauro Carvalho Chehab2010-05-101-2/+8
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Add support for sysfs addrmatch groupMauro Carvalho Chehab2010-05-101-103/+70
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Avoid printing a warning when debug is disabledMauro Carvalho Chehab2010-05-101-2/+1
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: We need to use list_for_each_entry_safe to avoid errorsMauro Carvalho Chehab2010-05-101-2/+3
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: change remove module strategyMauro Carvalho Chehab2010-05-101-20/+35
| | | | | | | | | | | | | | The old remove module stragegy didn't work on devices with multiple cores, since only one PCI device is used to open all mc's, due to Nehalem nature. Also, it were based at pdev value. However, this doesn't point to the pci device used at mci->dev. So, instead, it unregisters all devices at once, deleting them from the device list. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: remove static counter for max socketsMauro Carvalho Chehab2010-05-101-1/+0
| | | | | | | The number of sockets is now fully dynamic. Get rid of this obsolete var. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: at remove, don't remove all pci devices at onceMauro Carvalho Chehab2010-05-101-17/+19
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Fix a bug when printing error counts with RDIMMsMauro Carvalho Chehab2010-05-101-5/+8
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: a few fixes for multiple mc'sMauro Carvalho Chehab2010-05-101-9/+12
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: sanity check: print a warning if a mcelog is ignoredMauro Carvalho Chehab2010-05-101-1/+6
| | | | | | In thesis, the other mc controller should handle it. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: create one mc per socket/QPIMauro Carvalho Chehab2010-05-101-279/+228
| | | | | | | | | Instead of creating just one memory controller, create one per socket (e. g. per Quick Link Path Interconnect). This better reflects the Nehalem architecture. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* Dynamically allocate memory for PCI devicesMauro Carvalho Chehab2010-05-101-61/+114
| | | | | | | | | Instead of using a static table assuming always 2 CPU sockets, allocate space dynamically for Nehalem PCI devs. This patch is part of a series of patches that changes i7core_edac to allow more than 2 sockets and to properly report one memory controller per socket.
* i7core: temporary workaround to allow it to compile against 2.6.30Mauro Carvalho Chehab2010-05-101-2/+4
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Improve corrected_error_counts output for RDIMMMauro Carvalho Chehab2010-05-101-3/+3
| | | | | | | | | | | | | | | | | | | | Just cosmetics. instead of showing something like: socket 0, channel 2dimm0: 1 dimm1: 0 dimm2: 0 socket 1, channel 2dimm0: 0 dimm1: 0 dimm2: 0 Show: socket 0, channel 2 RDIMM0: 1 RDIMM1: 0 RDIMM2: 0 socket 0, channel 2 RDIMM0: 0 RDIMM1: 0 RDIMM2: 0 This is more synthetic and easier to parse. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Probe on Xeons earilerKeith Mannthey2010-05-101-13/+19
| | | | | | | | | | | | | | On the Xeon 55XX series cpus the pci deives are not exposed via acpi so we much explicitly probe them to make the usable as a Linux PCI device. This moves the detection of this state to before pci_register_driver is called. Its present position was not working on my systems, the driver would complain about not finding a specific device. This patch allows the driver to load on my systems. Signed-off-by: Keith Mannthey <kmannth@us.ibm.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core: Use registered memories per processorMauro Carvalho Chehab2010-05-101-16/+23
| | | | | | | | | | | | Instead of assuming that the entire machine has either registered or unregistered memories, do it at CPU socket based. While here, fix a bug at i7core_mce_output_error(), where the we're using m->cpu directly as if it would represent a socket. Instead, the proper socket_id is given by cpu_data[m->cpu].phys_proc_id. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> ---
* i7core_edac: Use Device 3 function 2 to report errors with RDIMM'sMauro Carvalho Chehab2010-05-101-30/+178
| | | | | | | | | | | | | | | | | Nehalem and upper chipsets provide an special device that has corrected memory error counters detected with registered dimms. This device is only seen if there are registered memories plugged. After this patch, on a machine fully equiped with RDIMM's, it will use the Device 3 function 2 to count corrected errors instead on relying at mcelog. For unregistered DIMMs, it will keep the old behavior, counting errors via mcelog. This patch were developed together with Keith Mannthey <kmannth@us.ibm.com> Signed-off-by: Keith Mannthey <kmannth@us.ibm.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Fix ecc enable shiftKeith Mannthey2010-05-101-1/+1
| | | | | | | | | | | | From: Keith Mannthey <kmannth@us.ibm.com> Simple correction to a shift value. ECC_ENABLED is bit 4 of MC_STATUS, Dev 3 Fun 0 Offset 0x4c This correctly identifies the state of the ECC at the machine. Signed-off-by: Keith Mannthey <kmannth@us.ibm.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Print an error message if pci register failsMauro Carvalho Chehab2010-05-101-1/+7
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: CodingSyle fixes/cleanupsMauro Carvalho Chehab2010-05-101-27/+23
| | | | | | No functional changes. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: fix error injectionMauro Carvalho Chehab2010-05-101-15/+12
| | | | | | | | | | | There were two stupid error injection bugs introduced by wrong cut-and-paste: one at socket store, and another at the error inject register. The last one were causing the code to not work at all. While here, adds debug messages to allow seeing what registers are being set while sending error injection. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: fix error codes for sysfs error injection interfaceMauro Carvalho Chehab2010-05-101-4/+4
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: some fixes at error injection codeMauro Carvalho Chehab2010-05-101-53/+51
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Some cleanups at displayed infoMauro Carvalho Chehab2010-05-101-12/+9
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core: remove some uneeded noisy debug messagesMauro Carvalho Chehab2010-05-101-4/+0
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core: add socket info at the debug msgMauro Carvalho Chehab2010-05-101-2/+2
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core: better document i7core_get_active_channels()Mauro Carvalho Chehab2010-05-101-1/+17
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core: fix get_devices routine for Xeon55xxMauro Carvalho Chehab2010-05-101-78/+108
| | | | | | | | | | | i7core_get_devices() were preparet to get just the first found device of each type. Due to that, on Xeon 55xx, only socket 1 were retrived. Rework i7core_get_devices() to clean it and to properly support Xeon 55xx. While here, fix a small typo. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core: enrich error information based on memory transaction typeMauro Carvalho Chehab2010-05-101-5/+27
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core: check if the memory error is fatal or non-fatalMauro Carvalho Chehab2010-05-101-3/+13
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core: fix probing on Xeon55xxMauro Carvalho Chehab2010-05-101-3/+20
| | | | | | | | | | | | | Xeon55xx fails to probe with this error message: EDAC DEBUG: in drivers/edac/i7core_edac.c, line at 1660: MC: drivers/edac/i7core_edac.c: i7core_init() EDAC i7core: Device not found: dev 00:00.0 PCI ID 8086:2c41 i7core_edac: probe of 0000:00:14.0 failed with error -22 This is due to the fact that, on Xeon35xx (and i7core), device 00.0 has PCI ID 8086:2c40. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: some fixes at memory error parserMauro Carvalho Chehab2010-05-101-8/+14
| | | | | | | | | | | m->bank is not related to the memory bank but, instead, to the MCA Error register bank. Fix it accordingly. While here, improves the comments for Nehalem bank. A later fix is needed, in order to get bank/rank information from MCA error log. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: decode mcelog error and send it via edac interfaceMauro Carvalho Chehab2010-05-101-22/+70
| | | | | | | | | | Enriches mcelog error by using the encoded information at MCE status and misc registers (IA32_MCx_STATUS, IA32_MCx_MISC). Some fixes are still needed here, in order to properly fill the EDAC fields. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: maps all sockets as if ther are one MC controllerMauro Carvalho Chehab2010-05-101-6/+7
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: add support for more than one MC socketMauro Carvalho Chehab2010-05-101-113/+213
| | | | | | | | | | | | | | Some Nehalem architectures have more than one MC socket. Socket 0 is located at bus 255. Currently, it is using up to 2 sockets, but increasing it to a larger number is just a matter of increasing MAX_SOCKETS definition. This seems to be required for properly support of Xeon 55xx. Still needs testing with Xeon 55xx. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Add a code to probe Xeon 55xx busMauro Carvalho Chehab2010-05-101-4/+13
| | | | | | | | | | | | | | | | | This code changes the detection procedure of i7core_edac. Instead of directly probing for MC registers, it probes for another register found on Nehalem. If found, it tries to pick the first MC PCI BUS. This should work fine with Xeon 35xx, but, on Xeon 55xx, this is at bus 254 and 255 that are not properly detected by the non-legacy PCI methods. The new detection code scans specifically at buses 254 and 255 for the Xeon 55xx devices. This code has not tested yet. After working, a change at the code will be needed, since the i7core is not yet ready for working with 2 sets of MC. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Adds write unlock to MC registersMauro Carvalho Chehab2010-05-101-3/+27
| | | | | | | | | | | | | | | | | The public Intel Xeon 5500 volume 2 datasheet describes, on page 53, session 2.6.7 a register that can lock/unlock Memory Controller the configuration register, called MC_CFG_CONTROL. Adds support for it in the hope that software error injection would work. With my tests with Xeon 35xx, there's still something missing. With a program that does sequencial bit writes at dev 0.0, sometimes, it produces error injection, after unblocking the MC_CFG_CONTROL (and, sometimes, it just locks my testing machine). I'll try later to discover by trial and error what's the register that solves this issue on Xeon 35xx. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Add edac_mce glueMauro Carvalho Chehab2010-05-101-2/+109
| | | | | | | | | | | | | | Adds a glue code to allow i7core to work with mcelog. With the glue, i7core registers itself on edac_mce. At mce, when an error is detected, it calls all registered drivers (in this case, i7core), for EDAC error handling. TODO: It currently just prints the MCE error log using about the same format as mce panic messages. The error message should be enhanced with mcelog userspace info and converted into the proper EDAC format, to feed the EDAC error counts. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: CodingStyle fixesMauro Carvalho Chehab2010-05-101-27/+32
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: fill csrows edac sysfs infoMauro Carvalho Chehab2010-05-101-16/+50
| | | | | | | csrows is still fake, since we can't identify its representation with Nehalem registers. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Memory info fixes and preparation for properly filling cswrow dataMauro Carvalho Chehab2010-05-101-9/+19
| | | | | | | | | | | | | | | | | | | | | | | | Now, memory size is properly displayed: EDAC i7core: DOD Max limits: DIMMS: 2, 1-ranked, 8-banked EDAC i7core: DOD Max rows x colums = 0x4000 x 0x400 EDAC i7core: Memory channel configuration: EDAC i7core: Ch0 phy rd0, wr0 (0x063f7c31): 2 ranks, UDIMMs EDAC i7core: dimm 0 (0x00000288) 1024 Mb offset: 0, numbank: 8, numrank: 1, numrow: 0x4000, numcol: 0x400 EDAC i7core: dimm 1 (0x00001288) 1024 Mb offset: 4, numbank: 8, numrank: 1, numrow: 0x4000, numcol: 0x400 EDAC i7core: Ch1 phy rd1, wr1 (0x063f7c31): 2 ranks, UDIMMs EDAC i7core: dimm 0 (0x00000288) 1024 Mb offset: 0, numbank: 8, numrank: 1, numrow: 0x4000, numcol: 0x400 EDAC i7core: Ch2 phy rd3, wr3 (0x063f7c31): 2 ranks, UDIMMs EDAC i7core: dimm 0 (0x00000288) 1024 Mb offset: 0, numbank: 8, numrank: 1, numrow: 0x4000, numcol: 0x400 Still, as the way to retrieve csrows info is not known, it does a mapping of what's available to csrows basic unit at edac core. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Get more info about the memory DIMMsMauro Carvalho Chehab2010-05-101-63/+107
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Add more information about each active dimmMauro Carvalho Chehab2010-05-101-13/+30
| | | | | | Thanks-to: Aristeu Rozanski <aris@redhat.com> for part of the code Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Improve error handlingMauro Carvalho Chehab2010-05-101-11/+21
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Properly fill struct csrow_infoMauro Carvalho Chehab2010-05-101-10/+38
| | | | | | Thanks-to: Aristeu Rozanski <aris@redhat.com> for part of the code Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
OpenPOWER on IntegriCloud