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* i7core_edac: Add additional tests for error detectionMauro Carvalho Chehab2010-05-101-60/+139
| | | | | | Properly check the number of channels and improve probing error detection Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Add a memory check routine, based on device 3 function 4Mauro Carvalho Chehab2010-05-101-7/+108
| | | | | | | | | | | | | | | | This function appears only on Xeon 5500 datasheet. Yet, testing with a Xeon 3503 showed that this is also implemented on other Nehalem processors. At the first read, MC_TEST_ERR_RCV1 and MC_TEST_ERR_RCV0 can contain any value. Modify CE error logic to update the error count only after the second read. An alternative approach would be to do a write at rcv0 and rcv1 registers, but it seemed better to keep they untouched, since BIOS might eventually assume that they are exclusive for their usage. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: need mci->edac_check, otherwise module removal doesn't workMauro Carvalho Chehab2010-05-101-4/+16
| | | | | | | There are some locking troubles with edac_core: if you don't declare an edac_check, module may suffer from soft lock. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: A few fixes at error injection codeMauro Carvalho Chehab2010-05-101-15/+55
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Show read/write virtual/physical channel associationMauro Carvalho Chehab2010-05-101-6/+27
| | | | Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Registers all supported MC functionsMauro Carvalho Chehab2010-05-101-86/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now, it will try to register on all supported Memory Controller functions. It should be noticed that dev3, function 2 is present only on chips with Registered DIMM's, according to the datasheet. So, the driver doesn't return -ENODEV is all functions but this one were successfully registered and enabled: EDAC i7core: Registered device 8086:2c18 fn=3 0 EDAC i7core: Registered device 8086:2c19 fn=3 1 EDAC i7core: Device not found: PCI ID 8086:2c1a (dev 3, func 2) EDAC i7core: Registered device 8086:2c1c fn=3 4 EDAC i7core: Registered device 8086:2c20 fn=4 0 EDAC i7core: Registered device 8086:2c21 fn=4 1 EDAC i7core: Registered device 8086:2c22 fn=4 2 EDAC i7core: Registered device 8086:2c23 fn=4 3 EDAC i7core: Registered device 8086:2c28 fn=5 0 EDAC i7core: Registered device 8086:2c29 fn=5 1 EDAC i7core: Registered device 8086:2c2a fn=5 2 EDAC i7core: Registered device 8086:2c2b fn=5 3 EDAC i7core: Registered device 8086:2c30 fn=6 0 EDAC i7core: Registered device 8086:2c31 fn=6 1 EDAC i7core: Registered device 8086:2c32 fn=6 2 EDAC i7core: Registered device 8086:2c33 fn=6 3 EDAC i7core: Driver loaded. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Add more status functions to EDAC driverMauro Carvalho Chehab2010-05-101-19/+95
| | | | | | | This patch were co-authored with Aristeu Rozanski. Signed-off-by: Aristeu Sergio <arozansk@redhat.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Add error insertion code for NehalemMauro Carvalho Chehab2010-05-101-8/+419
| | | | | | | | | Implements set_inject_error() with the low-level code needed to inject memory errors at Nehalem, and adds some sysfs nodes to allow error injection The next patch will add an API for error injection. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
* i7core_edac: Add an EDAC memory controller driver for Nehalem chipsetsMauro Carvalho Chehab2010-05-101-0/+462
This driver is meant to support i7 core/i7core extreme desktop processors and Xeon 35xx/55xx series with integrated memory controller. It is likely that it can be expanded in the future to work with other processor series based at the same Memory Controller design. For now, it has just a few MCH status reads. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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