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* dmaengine: Remove the context argument to the prep_dma_cyclic operationLaurent Pinchart2014-08-041-1/+1
| | | | | | | The argument is always set to NULL and never used. Remove it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: Use dma_zalloc_coherentJoe Perches2014-07-141-5/+3
| | | | | | | Use the zeroing function instead of dma_alloc_coherent & memset(,0,) Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mxs-dma: Use semaphores for cyclic DMAMarkus Pargmann2013-11-131-6/+35
| | | | | | | | | | | | | | | | | | | | | | | mxs dma channel hardware reset command is not reliable and can cause a channel stall. The only way to fix the channel stall is a DMA engine reset. To avoid channel resets we use the hardware semaphore counter. For each transmitted segment, the DMA channel will decrease the counter by one. To use this mechanism with cyclic DMA, we need to increase the semaphore counter with each completed DMA command in the interrupt handler. To avoid any interruptions between the DMA transfers, the semaphore counter is initialized with 2. This way the counter can be increased in the interrupt handler without an influence on the transfer of the DMA engine. When disabling the channel, we stop increasing the semaphore counter in the interrupt handler. This patch was tested on i.MX28 with the SAIF DMA channel. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mxs-dma: Update state after channel resetMarkus Pargmann2013-11-131-1/+3
| | | | | | | | | After a channel reset, the channel stops running automatically. The state update was missing so that a channel perperation right after a channel reset failed. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mxs-dma: Fix channel reset hardware bugMarkus Pargmann2013-11-131-2/+27
| | | | | | | | | | | | | | This is no official errata, but I noticed that the channel reset may stop working if the DMA state engine is in the READ_FLUSH state. This patch uses the channel debug1 register to wait for the DMA statemachine to leave the READ_FLUSH state. After that we can continue to reset the channel. Tested on i.MX28. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mxs-dma: Report correct residue for cyclic DMAMarkus Pargmann2013-11-131-1/+19
| | | | | | | | Use the channel's buffer address register to calculate correct residue value for tx_status. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mxs-dma: Cleanup interrupt handlerMarkus Pargmann2013-11-131-36/+60
| | | | | | | | | | | | The DMA interrupt handler uses its controll registers to handle all available channel interrupts it can find. This patch changes it to handle only one interrupt by directly mapping irq number to channel. It also includes a cleanup of the ctrl-register usage. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: mxs-dma: use DMA_COMPLETE for dma completion statusVinod Koul2013-10-251-3/+3
| | | | | | Acked-by: Dan Williams <dan.j.williams@intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mxs-dma: remove code left from generic DMA binding conversionShawn Guo2013-08-191-23/+0
| | | | | | | | | With all mxs-dma clients moved to use generic DMA helper, the code left from generic DMA binding conversion can be removed now. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* mxs-dma: remove useless variableAndy Shevchenko2013-08-051-3/+1
| | | | | | | last_used variable is applied only once, so, let's substitute it by its value. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mxs-dma: Staticize mxs_dma_xlateFabio Estevam2013-07-051-1/+1
| | | | | | | | | | Fix the following sparse warning: drivers/dma/mxs-dma.c:696:17: warning: symbol 'mxs_dma_xlate' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mxs-dma: move to generic device tree bindingShawn Guo2013-04-041-4/+66
| | | | | | | | | | | | | | | Update mxs-dma driver to adopt generic DMA device tree binding. It calls of_dma_controller_register() with mxs specific of_dma_xlate to get the generic DMA device tree helper support. Then DMA clients only need to call dma_request_slave_channel() for requesting a DMA channel from dmaengine. The existing way of requesting channel, clients directly call dma_request_channel(), still work there, and will be removed after all mxs-dma clients get converted to generic DMA device tree helper. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
* dma: mxs-dma: use devm_* managed functionsShawn Guo2013-04-041-30/+9
| | | | | | | Use devm_* managed functions to simplify probe() error handling. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
* dma: mxs-dma: Fix build warnings with W=1Fabio Estevam2013-01-081-4/+4
| | | | | | | | | | | | | | | | Fix the following warnings when building with W=1 option: drivers/dma/mxs-dma.c: In function 'mxs_dma_alloc_chan_resources': drivers/dma/mxs-dma.c:368:25: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] drivers/dma/mxs-dma.c: In function 'mxs_dma_prep_slave_sg': drivers/dma/mxs-dma.c:481:17: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] drivers/dma/mxs-dma.c:494:3: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] drivers/dma/mxs-dma.c:515:14: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] drivers/dma/mxs-dma.c: In function 'mxs_dma_prep_dma_cyclic': drivers/dma/mxs-dma.c:563:13: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* Merge branch 'next' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2012-10-101-6/+8
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull slave-dmaengine updates from Vinod Koul: "This time we have Andy updates on dw_dmac which is attempting to make this IP block available as PCI and platform device though not fully complete this time. We also have TI EDMA moving the dma driver to use dmaengine APIs, also have a new driver for mmp-tdma, along with bunch of small updates. Now for your excitement the merge is little unusual here, while merging the auto merge on linux-next picks wrong choice for pl330 (drivers/dma/pl330.c) and this causes build failure. The correct resolution is in linux-next. (DMA: PL330: Fix build error) I didn't back merge your tree this time as you are better than me so no point in doing that for me :)" Fixed the pl330 conflict as in linux-next, along with trivial header file conflicts due to changed includes. * 'next' of git://git.infradead.org/users/vkoul/slave-dma: (29 commits) dma: tegra: fix interrupt name issue with apb dma. dw_dmac: fix a regression in dwc_prep_dma_memcpy dw_dmac: introduce software emulation of LLP transfers dw_dmac: autoconfigure data_width or get it via platform data dw_dmac: autoconfigure block_size or use platform data dw_dmac: get number of channels from hardware if possible dw_dmac: fill optional encoded parameters in register structure dw_dmac: mark dwc_dump_chan_regs as inline DMA: PL330: return ENOMEM instead of 0 from pl330_alloc_chan_resources DMA: PL330: Remove redundant runtime_suspend/resume functions DMA: PL330: Remove controller clock enable/disable dmaengine: use kmem_cache_zalloc instead of kmem_cache_alloc/memset DMA: PL330: Set the capability of pdm0 and pdm1 as DMA_PRIVATE ARM: EXYNOS: Set the capability of pdm0 and pdm1 as DMA_PRIVATE dma: tegra: use list_move_tail instead of list_del/list_add_tail mxs/dma: Enlarge the CCW descriptor area to 4 pages dw_dmac: utilize slave_id to pass request line dmaengine: mmp_tdma: add dt support dmaengine: mmp-pdma support spi: davici - make davinci select edma ...
| * mxs/dma: Enlarge the CCW descriptor area to 4 pagesMarek Vasut2012-09-141-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of a large SPI flash, the amount of DMA descriptors available to the DMA driver is not large enough anymore. For example 8MB SPI flash now needs 129 descriptors to be transfered in one long read. There are currently 53 descriptors available in one PAGE_SIZE-big block. Enlarge the allocated descriptor area to four PAGE_SIZE blocks to fulfill such requirements. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dan Williams <djbw@fb.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* | dmaengine: Pass flags via device_prep_dma_cyclic() callbackPeter Ujfalusi2012-09-221-1/+1
|/ | | | | | | | | | | | | Change the parameter list of device_prep_dma_cyclic() so the DMA drivers can receive the flags coming from clients. This feature can be used during audio operation to disable all audio related interrupts when the DMA_PREP_INTERRUPT is cleared from the flags. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Vinod Koul <vinod.koul@linux.intel.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* dma: mxs-dma: Export missing symbols from mxs-dma.cAttila Kinali2012-07-161-0/+2
| | | | | | | | | | mxs-dma.c provides two functions mxs_dma_is_apbh and mxs_dma_is_apbx which are used at least in mxs-mmc.c. Building mxs-mmc as module fails due to those two symbols not being exported. Signed-off-by: Attila Kinali <attila@kinali.ch> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dma: enable mxs-dma for imx6qHuang Shijie2012-06-071-1/+0
| | | | | | | | | enable the mxs-dma for imx6q. Also remove the unused header file. Signed-off-by: Huang Shijie <shijie8@gmail.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2012-05-261-61/+127
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull arm-soc device tree conversions (part 2) from Olof Johansson: "These continue the device tree work from part 1, this set is for the tegra, mxs and imx platforms, all of which have dependencies on clock or pinctrl changes submitted earlier." Fix up trivial conflicts due to nearby changes in drivers/{gpio/gpio,i2c/busses/i2c}-mxs.c * tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (73 commits) ARM: dt: tegra: invert status=disable vs status=okay ARM: dt: tegra: consistent basic property ordering ARM: dt: tegra: sort nodes based on bus order ARM: dt: tegra: remove duplicate device_type property ARM: dt: tegra: consistenly use lower-case for hex constants ARM: dt: tegra: format regs properties consistently ARM: dt: tegra: gpio comment cleanup ARM: dt: tegra: remove unnecessary unit addresses ARM: dt: tegra: whitespace cleanup ARM: dt: tegra cardhu: fix typo in SDHCI node name ARM: dt: tegra: cardhu: register core regulator tps62361 ARM: dt: tegra30.dtsi: Add SMMU node ARM: dt: tegra20.dtsi: Add GART node ARM: dt: tegra30.dtsi: Add Memory Controller(MC) nodes ARM: dt: tegra20.dtsi: Add Memory Controller(MC) nodes ARM: dt: tegra: Add device tree support for AHB ARM: dts: enable audio support for imx28-evk ARM: dts: enable i2c device for imx28-evk i2c: mxs: add device tree probe support ARM: dts: enable mmc for imx28-evk ...
| * dma: mxs-dma: add device tree probe supportDong Aisheng2012-05-121-5/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Huang Shijie <b32955@freescale.com> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Vinod Koul <vinod.koul@intel.com>
| * dma: mxs-dma: make platform_device_id more genericShawn Guo2012-05-121-36/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rewrite mxs_dma_is_apbh and mxs_dma_is_apbx in order to support other SoCs like imx6q and reform the platform_device_id for the better further dt support. Cc: Dan Williams <dan.j.williams@intel.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Huang Shijie <b32955@freescale.com> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Vinod Koul <vinod.koul@intel.com>
| * dma: mxs-dma: let dma_is_apbh and apbh_is_old take parameterShawn Guo2012-05-121-12/+16
| | | | | | | | | | | | | | Let macros dma_is_apbh and apbh_is_old take mxs_dma as parameter to make the code easy to read. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * dma: mxs-dma: use global stmp_device functionalityDong Aisheng2012-05-121-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | This can get rid of the mach-dependency. Cc: Dan Williams <dan.j.williams@intel.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Huang Shijie <b32955@freescale.com> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Vinod Koul <vinod.koul@intel.com>
* | dmaengine: Use dma_sg_len(sg) instead of sg->lengthLars-Peter Clausen2012-05-111-3/+3
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sg->length may or may not contain the length of the dma region to transfer, depending on the architecture - dma_sg_len(sg) always will though. For the architectures which use the drivers modified by this patch it probably is the case that sg->length contains the dma transfer length. But to be consistent and future proof change them to use dma_sg_len. To quote Russel King: sg->length is meaningless to something performing DMA. In cases where sg_dma_len(sg) and sg->length are the same storage, then there's no problem. But scatterlists _can_ (and one some architectures) do split them - especially when you have an IOMMU which can allow you to combine a scatterlist into fewer entries. So, anything using sg->length for the size of a scatterlist's DMA transfer _after_ a call to dma_map_sg() is almost certainly buggy. The patch has been generated using the following coccinelle patch: <smpl> @@ struct scatterlist *sg; expression X; @@ -sg[X].length +sg_dma_len(&sg[X]) @@ struct scatterlist *sg; @@ -sg->length +sg_dma_len(sg) </smpl> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dma: mxs-dma: enable channel in device_issue_pending callShawn Guo2012-04-201-7/+3
| | | | | | | | | | | | | | Enable channel in device_issue_pending call, so that the order between cookie assignment and channel enabling can be ensured naturally. It fixes the mxs gpmi-nand breakage which is caused by the incorrect order of cookie assigning and channel enabling. Suggested-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Huang Shijie <b32955@freescale.com> Tested-by <samgandhi9@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* Merge tag 'for-linus-3.4' of git://git.infradead.org/mtd-2.6Linus Torvalds2012-03-301-5/+29
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MTD changes from David Woodhouse: - Artem's cleanup of the MTD API continues apace. - Fixes and improvements for ST FSMC and SuperH FLCTL NAND, amongst others. - More work on DiskOnChip G3, new driver for DiskOnChip G4. - Clean up debug/warning printks in JFFS2 to use pr_<level>. Fix up various trivial conflicts, largely due to changes in calling conventions for things like dmaengine_prep_slave_sg() (new inline wrapper to hide new parameter, clashing with rewrite of previously last parameter that used to be an 'append' flag, and is now a bitmap of 'unsigned long flags'). (Also some header file fallout - like so many merges this merge window - and silly conflicts with sparse fixes) * tag 'for-linus-3.4' of git://git.infradead.org/mtd-2.6: (120 commits) mtd: docg3 add protection against concurrency mtd: docg3 refactor cascade floors structure mtd: docg3 increase write/erase timeout mtd: docg3 fix inbound calculations mtd: nand: gpmi: fix function annotations mtd: phram: fix section mismatch for phram_setup mtd: unify initialization of erase_info->fail_addr mtd: support ONFI multi lun NAND mtd: sm_ftl: fix typo in major number. mtd: add device-tree support to spear_smi mtd: spear_smi: Remove default partition information from driver mtd: Add device-tree support to fsmc_nand mtd: fix section mismatch for doc_probe_device mtd: nand/fsmc: Remove sparse warnings and errors mtd: nand/fsmc: Add DMA support mtd: nand/fsmc: Access the NAND device word by word whenever possible mtd: nand/fsmc: Use dev_err to report error scenario mtd: nand/fsmc: Use devm routines mtd: nand/fsmc: Modify fsmc driver to accept nand timing parameters via platform mtd: fsmc_nand: add pm callbacks to support hibernation ...
| * mxs-dma : rewrite the last parameter of mxs_dma_prep_slave_sg()Huang Shijie2012-03-271-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [1] Background : The GPMI does ECC read page operation with a DMA chain consist of three DMA Command Structures. The middle one of the chain is used to enable the BCH, and read out the NAND page. The WAIT4END(wait for command end) is a comunication signal between the GPMI and MXS-DMA. [2] The current DMA code sets the WAIT4END bit at the last one, such as: +-----+ +-----+ +-----+ | cmd | ------------> | cmd | ------------------> | cmd | +-----+ +-----+ +-----+ ^ | | set WAIT4END here This chain works fine in the mx23/mx28. [3] But in the new GPMI version (used in MX50/MX60), the WAIT4END bit should be set not only at the last DMA Command Structure, but also at the middle one, such as: +-----+ +-----+ +-----+ | cmd | ------------> | cmd | ------------------> | cmd | +-----+ +-----+ +-----+ ^ ^ | | | | set WAIT4END here too set WAIT4END here If we do not set WAIT4END, the BCH maybe stalls in "ECC reading page" state. In the next ECC write page operation, a DMA-timeout occurs. This has been catched in the MX6Q board. [4] In order to fix the bug, rewrite the last parameter of mxs_dma_prep_slave_sg(), and use the dma_ctrl_flags: --------------------------------------------------------- DMA_PREP_INTERRUPT : append a new DMA Command Structrue. DMA_CTRL_ACK : set the WAIT4END bit for this DMA Command Structure. --------------------------------------------------------- [5] changes to the relative drivers: <1> For mxs-mmc driver, just use the new flags, do not change any logic. <2> For gpmi-nand driver, and use the new flags to set the DMA chain, especially for ecc read page. Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Vinod Koul <vinod.koul@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mxs-dma : move the mxs dma.h to a more common placeHuang Shijie2012-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the header to a more common place. The mxs dma engine is not only used in mx23/mx28, but also used in mx50/mx6q. It will also be used in the future chips. Rename it to mxs-dma.h, and create a new folder include/linux/fsl/ to store the Freescale's header files. change mxs-dma driver, mxs-mmc driver, gpmi-nand driver, mxs-saif driver to the new header file. Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Vinod Koul <vinod.koul@linux.intel.com> Acked-by: Chris Ball <cjb@laptop.org> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* | dmaengine: add context parameter to prep_slave_sg and prep_dma_cyclicAlexandre Bounine2012-03-211-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | Add context parameter to device_prep_slave_sg() and device_prep_dma_cyclic() interfaces to allow passing client/target specific information associated with the data transfer. Modify all affected DMA engine drivers. Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* | dmaengine: ensure all DMA engine drivers initialize their cookiesRussell King - ARM Linux2012-03-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure all DMA engine drivers initialize their cookies in the same way, so that they all behave in a similar fashion. This means their first issued cookie will be 2 rather than 1, and will increment to INT_MAX before returning 1 and starting over. In connection with this, Dan Williams said: > Russell King wrote: > > Secondly, some DMA engine drivers initialize the dma_chan cookie to 0, > > others to 1.  Is there a reason for this, or are these all buggy? > > I know that ioat and iop-adma expect 0 to mean "I have cleaned up this > descriptor and it is idle", and would break if zero was an in-flight > cookie value. The reserved usage of zero is an driver internal > concern, but I have no problem formalizing it as a reserved value. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* | dmaengine: provide a common function for completing a dma descriptorRussell King - ARM Linux2012-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Provide a common function to do the cookie mechanics for completing a DMA descriptor. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* | dmaengine: consolidate assignment of DMA cookiesRussell King - ARM Linux2012-03-131-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Everyone deals with assigning DMA cookies in the same way (it's part of the API so they should be), so lets consolidate the common code into a helper function to avoid this duplication. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* | dmaengine: add private header fileRussell King - ARM Linux2012-03-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a local private header file to contain definitions and declarations which should only be used by DMA engine drivers. We also fix linux/dmaengine.h to use LINUX_DMAENGINE_H to guard against multiple inclusion. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* | dmaengine: move last completed cookie into generic dma_chan structureRussell King - ARM Linux2012-03-131-3/+2
|/ | | | | | | | | | | | | | | Every DMA engine implementation declares a last completed dma cookie in their private dma channel structures. This is pointless, and forces driver specific code. Move this out into the common dma_chan structure. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* Merge branch 'next' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2012-01-171-40/+13
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.infradead.org/users/vkoul/slave-dma: (53 commits) ARM: mach-shmobile: specify CHCLR registers on SH7372 dma: shdma: fix runtime PM: clear channel buffers on reset dma/imx-sdma: save irq flags when use spin_lock in sdma_tx_submit dmaengine/ste_dma40: clear LNK on channel startup dmaengine: intel_mid_dma: remove legacy pm interface ASoC: mxs: correct 'direction' of device_prep_dma_cyclic dmaengine: intel_mid_dma: error path fix dmaengine: intel_mid_dma: locking and freeing fixes mtd: gpmi-nand: move to dma_transfer_direction mtd: fix compile error for gpmi-nand mmc: mxs-mmc: fix the dma_transfer_direction migration dmaengine: add DMA_TRANS_NONE to dma_transfer_direction dma: mxs-dma: Don't use CLKGATE bits in CTRL0 to disable DMA channels dma: mxs-dma: make mxs_dma_prep_slave_sg() multi user safe dma: mxs-dma: Always leave mxs_dma_init() with the clock disabled. dma: mxs-dma: fix a typo in comment DMA: PL330: Remove pm_runtime_xxx calls from pl330 probe/remove video i.MX IPU: Fix display connections i.MX IPU DMA: Fix wrong burstsize settings dmaengine/ste_dma40: allow fixed physical channel ... Fix up conflicts in drivers/dma/{Kconfig,mxs-dma.c,pl330.c} The conflicts looked pretty trivial, but I'll ask people to verify them.
| * dmaengine: add DMA_TRANS_NONE to dma_transfer_directionShawn Guo2011-12-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before dma_transfer_direction was introduced to replace dma_data_direction, some dmaengine device uses DMA_NONE of dma_data_direction for some talk with its client drivers. The mxs-dma and its clients mxs-mmc and gpmi-nand are such case. This patch adds DMA_TRANS_NONE to dma_transfer_direction and migrate the DMA_NONE use in mxs-dma to it. It also fixes the compile warning below. CC drivers/dma/mxs-dma.o drivers/dma/mxs-dma.c: In function ‘mxs_dma_prep_slave_sg’: drivers/dma/mxs-dma.c:420:16: warning: comparison between ‘enum dma_transfer_direction’ and ‘enum dma_data_direction’ Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dma: mxs-dma: Don't use CLKGATE bits in CTRL0 to disable DMA channelsLothar Waßmann2011-12-231-28/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is how the original Freescale code (unintentionally) worked, because the code path which would have asserted the CLKGATE bit was never actually reached in their code. This fixes the nefarious "DMA timout" bug when multiple DMA channels (e.g. GPMI NAND and MMC) are used at the same time. If a better fix for this problem should be found, the clkgate handling could be reinstated. See http://lists.infradead.org/pipermail/linux-arm-kernel/2011-September/065228.html Also reverse the order of mxs_dma_disable_chan() and mxs_dma_reset_chan() in mxs_dma_control() because mxs_dma_reset_chan() can only work when the DMA channel is enabled. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dma: mxs-dma: make mxs_dma_prep_slave_sg() multi user safeLothar Waßmann2011-12-231-1/+4
| | | | | | | | | | | | | | | | Using a static variable for counting the number of CCWs attached to a DMA channel when appending a new descriptor is not multi user safe. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dma: mxs-dma: Always leave mxs_dma_init() with the clock disabled.Lothar Waßmann2011-12-231-5/+2
| | | | | | | | | | | | | | | | | | | | There is no need to have the clock enabled all the time the driver is loaded. It will be enabled anyway in mxs_dma_alloc_chan_resources() when a channel is actually going to be used. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dma: mxs-dma: fix a typo in commentLothar Waßmann2011-12-231-1/+1
| | | | | | | | | | Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dmaengine: move drivers to dma_transfer_directionVinod Koul2011-10-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fixup usage of dma direction by introducing dma_transfer_direction, this patch moves dma/drivers/* to use new enum Cc: Jassi Brar <jaswinder.singh@linaro.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Mika Westerberg <mika.westerberg@iki.fi> Cc: H Hartley Sweeten <hartleys@visionengravers.com> Cc: Li Yang <leoli@freescale.com> Cc: Zhang Wei <zw@zh-kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Shawn Guo <shawn.guo@freescale.com> Cc: Yong Wang <yong.y.wang@intel.com> Cc: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com> Cc: Boojin Kim <boojin.kim@samsung.com> Cc: Barry Song <Baohua.Song@csr.com> Acked-by: Mika Westerberg <mika.westerberg@iki.fi> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* | dma: mxs-dma: convert to clk_prepare/clk_unprepareShawn Guo2011-12-281-4/+4
|/ | | | | | | | | The patch converts mxs-dma driver to clk_prepare/clk_unprepare by using helper functions clk_prepare_enable/clk_disable_unprepare. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
* mxs-dma: enable CLKGATE before accessing registersLothar Waßmann2011-08-161-21/+24
| | | | | | | | | After calling mxs_dma_disable_chan() for a channel, that channel becomes unusable because some controller registers can only be written when the clock is enabled via CLKGATE. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* ARM: mxs-dma: reset after disable channelDong Aisheng2011-07-261-0/+1
| | | | | | | | | | We met some channels in abnormal state after disable. Reset it to get a clean state. Signed-off-by: Dong Aisheng <b29396@freescale.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: mxs-dma: fix unterminated platform_device_id tableAxel Lin2011-07-261-0/+2
| | | | | Signed-off-by: Axel Lin <axel.lin@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: mxs-dma: skip request_irq for NO_IRQShawn Guo2011-07-141-4/+6
| | | | | | | | | | | | | | | | | In general, the mxs-dma users get separate irq for each channel, but gpmi is special one which has only one irq shared by all gpmi channels. It causes mxs_dma channel allocation function fail for all other gpmi channels except the first one calling into the function. The patch gets request_irq call skipped for NO_IRQ case, and leaves this gpmi specific quirk to gpmi driver to sort out. It will fix above problem if gpmi driver sets chan_irq as gpmi irq for only one channel and NO_IRQ for all the rest channels. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: mxs-dma: add dma support for i.MX23/28Shawn Guo2011-03-021-0/+724
This patch adds dma support for Freescale MXS-based SoC i.MX23/28, including apbh-dma and apbx-dma. * apbh-dma and apbx-dma are supported in the driver as two mxs-dma instances. * apbh-dma is different between mx23 and mx28, hardware version register is used to differentiate. * mxs-dma supports pio function besides data transfer. The driver uses dma_data_direction DMA_NONE to identify the pio mode, and steals sgl and sg_len to get pio words and numbers from clients. * mxs dmaengine has some very specific features, like sense function and the special NAND support (nand_lock, nand_wait4ready). These are too specific to implemented in generic dmaengine driver. * The driver refers to imx-sdma and only a single descriptor is statically assigned to each channel. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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