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* Merge tag 'powerpc-4.4-1' of ↵Linus Torvalds2015-11-052-220/+1136
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc updates from Michael Ellerman: - Kconfig: remove BE-only platforms from LE kernel build from Boqun Feng - Refresh ps3_defconfig from Geoff Levand - Emit GNU & SysV hashes for the vdso from Michael Ellerman - Define an enum for the bolted SLB indexes from Anshuman Khandual - Use a local to avoid multiple calls to get_slb_shadow() from Michael Ellerman - Add gettimeofday() benchmark from Michael Neuling - Avoid link stack corruption in __get_datapage() from Michael Neuling - Add virt_to_pfn and use this instead of opencoding from Aneesh Kumar K.V - Add ppc64le_defconfig from Michael Ellerman - pseries: extract of_helpers module from Andy Shevchenko - Correct string length in pseries_of_derive_parent() from Nathan Fontenot - Free the MSI bitmap if it was slab allocated from Denis Kirjanov - Shorten irq_chip name for the SIU from Christophe Leroy - Wait 1s for secondaries to enter OPAL during kexec from Samuel Mendoza-Jonas - Fix _ALIGN_* errors due to type difference, from Aneesh Kumar K.V - powerpc/pseries/hvcserver: don't memset pi_buff if it is null from Colin Ian King - Disable hugepd for 64K page size, from Aneesh Kumar K.V - Differentiate between hugetlb and THP during page walk from Aneesh Kumar K.V - Make PCI non-optional for pseries from Michael Ellerman - Individual System V IPC system calls from Sam bobroff - Add selftest of unmuxed IPC calls from Michael Ellerman - discard .exit.data at runtime from Stephen Rothwell - Delete old orphaned PrPMC 280/2800 DTS and boot file, from Paul Gortmaker - Use of_get_next_parent to simplify code from Christophe Jaillet - Paginate some xmon output from Sam bobroff - Add some more elements to the xmon PACA dump from Michael Ellerman - Allow the tm-syscall selftest to build with old headers from Michael Ellerman - Run EBB selftests only on POWER8 from Denis Kirjanov - Drop CONFIG_TUNE_CELL in favour of CONFIG_CELL_CPU from Michael Ellerman - Avoid reference to potentially freed memory in prom.c from Christophe Jaillet - Quieten boot wrapper output with run_cmd from Geoff Levand - EEH fixes and cleanups from Gavin Shan - Fix recursive fenced PHB on Broadcom shiner adapter from Gavin Shan - Use of_get_next_parent() in of_get_ibm_chip_id() from Michael Ellerman - Fix section mismatch warning in msi_bitmap_alloc() from Denis Kirjanov - Fix ps3-lpm white space from Rudhresh Kumar J - Fix ps3-vuart null dereference from Colin King - nvram: Add missing kfree in error path from Christophe Jaillet - nvram: Fix function name in some errors messages, from Christophe Jaillet - drivers/macintosh: adb: fix misleading Kconfig help text from Aaro Koskinen - agp/uninorth: fix a memleak in create_gatt_table from Denis Kirjanov - cxl: Free virtual PHB when removing from Andrew Donnellan - scripts/kconfig/Makefile: Allow KBUILD_DEFCONFIG to be a target from Michael Ellerman - scripts/kconfig/Makefile: Fix KBUILD_DEFCONFIG check when building with O= from Michael Ellerman - Freescale updates from Scott: Highlights include 64-bit book3e kexec/kdump support, a rework of the qoriq clock driver, device tree changes including qoriq fman nodes, support for a new 85xx board, and some fixes. - MPC5xxx updates from Anatolij: Highlights include a driver for MPC512x LocalPlus Bus FIFO with its device tree binding documentation, mpc512x device tree updates and some minor fixes. * tag 'powerpc-4.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (106 commits) powerpc/msi: Fix section mismatch warning in msi_bitmap_alloc() powerpc/prom: Use of_get_next_parent() in of_get_ibm_chip_id() powerpc/pseries: Correct string length in pseries_of_derive_parent() powerpc/e6500: hw tablewalk: make sure we invalidate and write to the same tlb entry powerpc/mpc85xx: Add FSL QorIQ DPAA FMan support to the SoC device tree(s) powerpc/mpc85xx: Create dts components for the FSL QorIQ DPAA FMan powerpc/fsl: Add #clock-cells and clockgen label to clockgen nodes powerpc: handle error case in cpm_muram_alloc() powerpc: mpic: use IRQCHIP_SKIP_SET_WAKE instead of redundant mpic_irq_set_wake powerpc/book3e-64: Enable kexec powerpc/book3e-64/kexec: Set "r4 = 0" when entering spinloop powerpc/booke: Only use VIRT_PHYS_OFFSET on booke32 powerpc/book3e-64/kexec: Enable SMP release powerpc/book3e-64/kexec: create an identity TLB mapping powerpc/book3e-64: Don't limit paca to 256 MiB powerpc/book3e/kdump: Enable crash_kexec_wait_realmode powerpc/book3e: support CONFIG_RELOCATABLE powerpc/booke64: Fix args to copy_and_flush powerpc/book3e-64: rename interrupt_end_book3e with __end_interrupts powerpc/e6500: kexec: Handle hardware threads ...
| * Merge branch 'clock' into HEADScott Wood2015-10-272-220/+1136
| |\ | | | | | | | | | | | | | | | This is a major overhaul of the clk-qoriq driver, which I'm merging via PPC with Stephen Boyd's ack in order to apply subsequent PPC patches that depend on it.
| | * clk: qoriq: Add ls1043a support.Hou Zhiqiang2015-10-271-0/+38
| | | | | | | | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * clk: qoriq: Fix wrong data in p2041_cmux_grp2Scott Wood2015-10-221-2/+2
| | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * clk: qoriq: Add ls2080a support.Scott Wood2015-10-212-10/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080A is the first implementation of the chassis 3 clockgen, which has a different register layout than previous chips. It is also little endian, unlike previous chips. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: qoriq: Move chip-specific knowledge into driverScott Wood2015-10-211-221/+1040
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree should describe the chips (or chip-like subblocks) in the system, but it generally does not describe individual registers -- it should identify, rather than describe, a programming interface. This has not been the case with the QorIQ clockgen nodes. The knowledge of what each bit setting of CLKCnCSR means is encoded in three places (binding, pll node, and mux node), and the last also needs to know which options are valid on a particular chip. All three of these locations are considered stable ABI, making it difficult to fix mistakes (of which I have found several), much less refactor the abstraction to be able to address problems, limitations, or new chips. Under the current binding, a pll clock specifier of 2 means that the PLL is divided by 4 -- and the driver implements this, unless there happen to be four clock-output-names rather than 3, in which case it interprets it as PLL divided by 3. This does not appear in the binding documentation at all. That hack is now considered stable ABI. The current device tree nodes contain errors, such as saying that T1040 can set a core clock to PLL/4 when only PLL and PLL/2 are options. The current binding also ignores some restrictions on clock selection, such as p5020's requirement that if a core uses the "wrong" PLL, that PLL must be clocked lower than the "correct" PLL and be at most 80% of the rated CPU frequency. Possibly because of the lack of the ability to express such nuance in the binding, some valid options are omitted from the device trees, such as the ability on p4080 to run cores 0-3 from PLL3 and cores 4-7 from PLL1 (again, only if they are at most 80% of rated CPU frequency). This omission, combined with excessive caution in the cpufreq driver (addressed in a subsequent patch), means that currently on a 1500 MHz p4080 with typical PLL configuration, cpufreq can lower the frequency to 1200 MHz on half the CPUs and do nothing on the others. With this patchset, all CPUs can be lowered to 1200 MHz on a rev2 p4080, and on a rev3 p4080 half can be lowered to 750 MHz and the other half to 600 MHz. The current binding only deals with CPU clocks. To describe FMan in the device tree, we need to describe its clock. Some chips have additional muxes that work like the CPU muxes, but are not described in the device tree. Others require inspecting the Reset Control Word to determine which PLL is used. Rather than continue to extend this mess, replace it. Have the driver bind to the chip-specific clockgen compatible, and keep the detailed description of quirky chip variations in the driver, where it can be easily fixed, refactored, and extended. Older device trees will continue to work (including a workaround for old ls1021a device trees that are missing compatible and reg in the clockgen node, which even the old binding required). The pll/mux details in old device trees will be ignored, but "clocks" properties pointing at the old nodes will still work, and be directed at the corresponding new clock. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* | | Merge tag 'clk-for-linus-20151104' of ↵Linus Torvalds2015-11-05107-999/+7515
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The majority of the changes are driver updates and new device support. The core framework is mostly unchanged this time around, with only a couple patches to expose a clk provider API and make getting clk parent names from DT more robust. Driver updates: - Support for clock controllers found on Broadcom Northstar SoCs and bcm2835 SoC - Support for Allwinner audio clocks - A few cleanup patches for Tegra drivers and support for the highest DFLL frequencies on Tegra124 - Samsung exynos7 fixes and improvements - i.Mx SoC updates to add a few missing clocks and keep debug uart clocks on during kernel intialization - Some mediatek cleanups and support for more subsystem clocks - Support for msm8916 gpu/audio clocks and qcom's GDSC power domain controllers - A new driver for the Silabs si514 clock chip" * tag 'clk-for-linus-20151104' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (143 commits) clk: qcom: msm8960: Fix dsi1/2 halt bits clk: lpc18xx-cgu: fix potential system hang when disabling unused clocks clk: lpc18xx-ccu: fix potential system hang when disabling unused clocks clk: Add clk_hw_is_enabled() for use by clk providers clk: Add stubs for of_clk_*() APIs when CONFIG_OF=n clk: versatile-icst: fix memory leak clk: Remove clk_{register,unregister}_multiplier() clk: iproc: define Broadcom NS2 iProc clock binding clk: iproc: define Broadcom NSP iProc clock binding clk: ns2: add clock support for Broadcom Northstar 2 SoC clk: iproc: Separate status and control variables clk: iproc: Split off dig_filter clk: iproc: Add PLL base write function clk: nsp: add clock support for Broadcom Northstar Plus SoC clk: iproc: Add PWRCTRL support clk: cygnus: Convert all macros to all caps ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled clk: imx31: add missing of_node_put clk: imx27: add missing of_node_put clk: si5351: add missing of_node_put ...
| * | | clk: qcom: msm8960: Fix dsi1/2 halt bitsStephen Boyd2015-10-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The halt bits for these clocks seem wrong. I get the following warning while booting on an msm8960-cdp: WARNING: CPU: 0 PID: 1 at drivers/clk/qcom/clk-branch.c:97 clk_branch_toggle+0xd0/0x138() dsi1_clk status stuck at 'on' Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.3.0-rc3-00113-g5532cfb567fe #110 Hardware name: Qualcomm (Flattened Device Tree) [<c0216984>] (unwind_backtrace) from [<c02138f8>] (show_stack+0x10/0x14) [<c02138f8>] (show_stack) from [<c04a525c>] (dump_stack+0x70/0xbc) [<c04a525c>] (dump_stack) from [<c0223c70>] (warn_slowpath_common+0x78/0xb4) [<c0223c70>] (warn_slowpath_common) from [<c0223d40>] (warn_slowpath_fmt+0x30/0x40) [<c0223d40>] (warn_slowpath_fmt) from [<c05fc2dc>] (clk_branch_toggle+0xd0/0x138) [<c05fc2dc>] (clk_branch_toggle) from [<c05f3f3c>] (clk_disable_unused_subtree+0x98/0x1b0) [<c05f3f3c>] (clk_disable_unused_subtree) from [<c05f3ec4>] (clk_disable_unused_subtree+0x20/0x1b0) [<c05f3ec4>] (clk_disable_unused_subtree) from [<c05f5474>] (clk_disable_unused+0x58/0xd8) [<c05f5474>] (clk_disable_unused) from [<c0209710>] (do_one_initcall+0xac/0x1ec) [<c0209710>] (do_one_initcall) from [<c0991db4>] (kernel_init_freeable+0x11c/0x1e8) [<c0991db4>] (kernel_init_freeable) from [<c0727ae0>] (kernel_init+0x8/0xec) [<c0727ae0>] (kernel_init) from [<c0210238>] (ret_from_fork+0x14/0x3c) Fix the status bits and the errors go away. Fixes: 5532cfb567fe ("clk: qcom: mmcc-8960: Add DSI related clocks") Acked-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: lpc18xx-cgu: fix potential system hang when disabling unused clocksJoachim Eastwood2015-10-261-3/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock consumer (CCU) of the CGU must be able to check if a CGU base clock is really running since access to the CCU registers requires a running base clock. Access with a disabled base clock will cause the system to hang. Fix this issue by adding code that check if the parent clock is running in the is_enabled clk_ops callback. Since certain clocks can be cascaded this must be added to all clock gates. The hang would occur if the boot ROM or boot loader didn't setup and enable the USB0 clock. Then when the clk framework tried to access the CCU register it would hang the system. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: lpc18xx-ccu: fix potential system hang when disabling unused clocksJoachim Eastwood2015-10-261-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CCU branch clock register must only be accessed while the base (parent) clock is running. Access with a disabled base clock will cause the system to hang. Fix this issue by adding code that check if the parent clock is running in the is_enabled clk_ops callback. This hang would occur when disabling unused clocks after AMBA runtime pm had already disabled some of the clocks. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: Add clk_hw_is_enabled() for use by clk providersJoachim Eastwood2015-10-261-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clk_hw_is_enabled() to the provider APIs so clk providers can use a struct clk_hw instead of a struct clk to check if a clk is enabled or not. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: versatile-icst: fix memory leakLinus Walleij2015-10-231-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A static code checker found a memory leak in the Versatile ICST code. Fix it. Fixes: a183da637c52 "clk: versatile: respect parent rate in ICST clock" Reported-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: Remove clk_{register,unregister}_multiplier()Stephen Boyd2015-10-231-51/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These APIs aren't used, so remove them. This can be reverted if we get a user at some point. Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com> Suggested-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | Merge branch 'clk-iproc' into clk-nextStephen Boyd2015-10-218-158/+638
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-iproc: clk: iproc: define Broadcom NS2 iProc clock binding clk: iproc: define Broadcom NSP iProc clock binding clk: ns2: add clock support for Broadcom Northstar 2 SoC clk: iproc: Separate status and control variables clk: iproc: Split off dig_filter clk: iproc: Add PLL base write function clk: nsp: add clock support for Broadcom Northstar Plus SoC clk: iproc: Add PWRCTRL support clk: cygnus: Convert all macros to all caps ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
| | * | | clk: ns2: add clock support for Broadcom Northstar 2 SoCJon Mason2015-10-213-1/+290
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Broadcom Northstar 2 SoC is architected under the iProc architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, LCPLL DDR, LCPLL Ports, all derived from an onboard crystal. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * | | clk: iproc: Separate status and control variablesJon Mason2015-10-212-40/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some PLLs have separate registers for Status and Control. The means the pll_base needs to be split into 2 new variables, so that those PLLs can specify device tree registers for those independently. Also, add a new driver flag to identify this presence of the split, and let the driver know that additional registers need to be used. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * | | clk: iproc: Split off dig_filterJon Mason2015-10-214-17/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PLL loop filter/gain can be located in a separate register on some SoCs. Split these off into a separate variable, so that an offset can be added if necessary. Also, make the necessary modifications to the Cygnus and NSP drivers for this change. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * | | clk: iproc: Add PLL base write functionJon Mason2015-10-211-47/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All writes to the PLL base address must be flushed if the IPROC_CLK_NEEDS_READ_BACK flag is set. If we add a function to make the necessary write and reads, we can make sure that any future code which makes PLL base writes will do the correct thing. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * | | clk: nsp: add clock support for Broadcom Northstar Plus SoCJon Mason2015-10-212-0/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Broadcom Northstar Plus SoC is architected under the iProc architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all derived from an onboard crystal. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * | | clk: iproc: Add PWRCTRL supportJon Mason2015-10-212-17/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some iProc SoC clocks use a different way to control clock power, via the PWRDWN bit in the PLL control register. Since the PLL control register is used to access the PWRDWN bit, there is no need for the pwr_base when this is being used. A new flag, IPROC_CLK_EMBED_PWRCTRL, has been added to identify this usage. We can use the AON interface to write the values to enable/disable PWRDOWN. Signed-off-by: Jon Mason <jonmason@broadcom.com> [sboyd@codeaurora.org: Remove useless parentheses] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * | | clk: cygnus: Convert all macros to all capsJon Mason2015-10-211-73/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The macros that are being used to initialize the values of the clk structures should be all caps. Find and replace all of them with their relevant counterparts. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * | | ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabledArnd Bergmann2015-10-211-3/+1
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_CYGNUS is set but CONFIG_COMMON_CLK_IPROC is disabled, the following link failures are caused: drivers/built-in.o: In function `cygnus_armpll_init': :(.init.text+0x1d290): undefined reference to `iproc_armpll_setup' drivers/built-in.o: In function `cygnus_genpll_clk_init': :(.init.text+0x1d2c4): undefined reference to `iproc_pll_clk_setup' drivers/built-in.o: In function `cygnus_lcpll0_clk_init': :(.init.text+0x1d304): undefined reference to `iproc_pll_clk_setup' drivers/built-in.o: In function `cygnus_mipipll_clk_init': :(.init.text+0x1d344): undefined reference to `iproc_pll_clk_setup' drivers/built-in.o: In function `cygnus_asiu_init': :(.init.text+0x1d370): undefined reference to `iproc_asiu_setup' It is fixed it by always selecting COMMON_CLK_IPROC from ARCH_BCM_IPROC, and making COMMON_CLK_IPROC a silent option (thus preventing it from being erroneously disabled by a user). Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | Merge tag 'sunxi-clocks-for-4.4' of ↵Stephen Boyd2015-10-217-0/+528
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock additions for 4.4 from Maxime Ripard: - Support for the Audio PLL and child clocks - Support for the A33 AHB gates - New clk-multiplier generic driver * tag 'sunxi-clocks-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi: mod1 clock support clk: sunxi: codec clock support clk: sunxi: pll2: Add A13 support clk: sunxi: Add a driver for the PLL2 clk: Add a basic multiplier clock clk: sunxi: Add A33 gates support
| | * | | clk: sunxi: mod1 clock supportEmilio López2015-10-212-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The module 1 type of clocks consist of a gate and a mux and are used on the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or SPDIF. This commit adds support for them on the sunxi clock driver. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
| | * | | clk: sunxi: codec clock supportEmilio López2015-10-212-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The codec clock on sun4i, sun5i and sun7i is a simple gate with PLL2 as parent. Add a driver for such a clock. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
| | * | | clk: sunxi: pll2: Add A13 supportMaxime Ripard2015-10-211-5/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A13, unlike the A10 and A20, doesn't use a pass-through exception for the 0 value in the pre and post dividers, but increments all the values written in the register by one. Add an exception for both these cases to handle them nicely. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
| | * | | clk: sunxi: Add a driver for the PLL2Maxime Ripard2015-10-212-0/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PLL2 on the A10 and later SoCs is the clock used for all the audio related operations. This clock has a somewhat complex output tree, with three outputs (2X, 4X and 8X) with a fixed divider from the base clock, and an output (1X) with a post divider. However, we can simplify things since the 1X divider can be fixed, and we end up by having a base clock not exposed to any device (or at least directly, since the 4X output doesn't have any divider), and 4 fixed divider clocks that will be exposed. This clock seems to have been introduced, at least in this form, in the revision B of the A10, but we don't have any information on the clock used on the revision A. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
| | * | | clk: Add a basic multiplier clockMaxime Ripard2015-10-212-0/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some clocks are using a multiplier component, however, unlike their mux, gate or divider counterpart, these factors don't have a basic clock implementation. This leads to code duplication across platforms that want to use that kind of clocks, and the impossibility to use the composite clocks with such a clock without defining your own rate operations. Create such a driver in order to remove these issues, and hopefully factor the implementations, reducing code size across platforms and consolidating the various implementations. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
| | * | | clk: sunxi: Add A33 gates supportMaxime Ripard2015-09-181-0/+2
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A33 gates are different from the A23 ones, add a new hook to simple gates to handle this clock Reported-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | clk: imx31: add missing of_node_putJulia Lawall2015-10-211-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for_each_compatible_node performs an of_node_get on each iteration, so a break out of the loop requires an of_node_put. The semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e; @@ for_each_compatible_node(n,...) { ... ( of_node_put(n); | e = n | + of_node_put(n); ? break; ) ... } ... when != n // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: imx27: add missing of_node_putJulia Lawall2015-10-211-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for_each_compatible_node performs an of_node_get on each iteration, so a break out of the loop requires an of_node_put. The semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e; @@ for_each_compatible_node(n,...) { ... ( of_node_put(n); | e = n | + of_node_put(n); ? break; ) ... } ... when != n // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: si5351: add missing of_node_putJulia Lawall2015-10-211-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for_each_child_of_node performs an of_node_get on each iteration, so a break out of the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ expression root,e; local idexpression child; @@ for_each_child_of_node(root, child) { ... when != of_node_put(child) when != e = child ( return child; | + of_node_put(child); ? return ...; ) ... } // </smpl> The resulting puts were manually moved to the end of the function for conciseness. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: add missing of_node_putJulia Lawall2015-10-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for_each_matching_node_and_match performs an of_node_get on each iteration, so a break out of the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ expression e1,e2,e; local idexpression np; @@ for_each_matching_node_and_match(np, e1, e2) { ... when != of_node_put(np) when != e = np ( return np; | + of_node_put(np); ? return ...; ) ... } // </smpl> Besides the problem identified by the semantic patch, this patch adds an of_node_get in front of saving np in a field of parent, to account for the fact that this value will be put on going on to the next element in the iteration, and then adds of_node_puts in the two loops where the parent pointer can be freed. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: iproc: Fix PLL output frequency calculationSimran Rai2015-10-211-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch affects the clocks that use fractional ndivider in their PLL output frequency calculation. Instead of 2^20 divide factor, the clock's ndiv integer shift was used. Fixed the bug by replacing ndiv integer shift with 2^20 factor. Signed-off-by: Simran Rai <ssimran@broadcom.com> Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support") Cc: <stable@vger.kernel.org> # v4.1+ Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * | | clk: berlin: bg2: remove CLK_IGNORE_UNUSED flag for sdio clkJisheng Zhang2015-10-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clocks' properties have been already properly set, so there's no need to set this flag for sdio0 and sdio1 clk any more. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * | | clk: berlin: bg2q: remove CLK_IGNORE_UNUSED flag for sdio clkJisheng Zhang2015-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we have added the necessary two clks' properties in dts, we can remove the "sdio" clk's CLK_IGNORE_UNUSED flag now. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * | | Merge tag 'tegra-for-4.4-clk' of ↵Michael Turquette2015-10-207-113/+163
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk: tegra: Changes for v4.4-rc1 This contains a patch that allows the DFLL to use clock rates higher than 2^31-1 Hz by using the ->determine_rate() operation instead of the ->round_rate() operation. Other than that there's a couple of cleanups in preparation for Tegra210 support.
| | * | | clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein2015-10-205-11/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tegra_audio_clk_init was written expecting a single PLL to be passed in directly. Change this to accept an array which will allow for supporting multiple plls and specifying specific data about them, like their parent, which may change over time. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | clk: tegra: Update struct tegra_clk_pll_params kerneldocThierry Reding2015-10-201-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Benson Leung pointed out that the kerneldoc for this structure has become stale. Update the field descriptions to match the structure content. Reported-by: Benson Leung <bleung@chromium.org> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | clk: tegra: Fix comments for structure definitionsRhyland Klein2015-10-201-37/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some fields moved from the tegra_clk_pll struct to the tegra_pll_params struct. Update the struct comments to reflect where the fields really are. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | clk: tegra: dfll: Monitor code is DEBUG_FS onlyThierry Reding2015-10-201-50/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The monitor code is used with DEBUG_FS only, so move it into the corresponding #ifdef block to avoid potential compiler warnings. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | clk: tegra: Unlock top rates for Tegra124 DFLL clockMikko Perttunen2015-09-152-14/+8
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new determine_rate prototype allows for clock rates exceeding 2^31-1 Hz to be used. Switch the DFLL clock to use determine_rate instead of round_rate and unlock the top rates supported by the Tegra124. Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | clk: keystone: fix a trivial typoGeliang Tang2015-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | s/regsiter/register/ Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: mvebu: Use of_clk_get_parent_name()Stephen Boyd2015-10-161-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e79b202c632f24f49f2eb9459b88b5fd9e332263. Now that we use of_clk_get() inside of_clk_get_parent_name() we can safely use it here. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: qcom: mmcc-8960: Add DSI related clocksArchit Taneja2015-10-161-0/+404
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add rcg and branch clk structs for DSI1 and DSI2 blocks found in MSM8960 and APQ8064. Each DSI instance has 4 pairs of rcg and branch clocks. Populate arrays mmcc_msm8960_clks and mmcc_apq8064_clks with these clocks. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: qcom: clk-rcg: Add customized clk_ops for DSI RCGsArchit Taneja2015-10-162-0/+233
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DSI specific RCG clocks required customized clk_ops. There are a total of 4 RCGs per DSI block: DSI, BYTE, ESC and PIXEL. There are a total of 2 clocks coming from the DSI PLL, which serve as inputs to these RCGs. The BYTE and ESC RCGs are fed by one of the post dividers of DSI1 or DSI2 PLLs, and the DSI and PIXEL RCGs are fed by another divider of the PLL. In each of the 2 groups above, only one of the clocks sets its parent. These are BYTE RCG and DSI RCG for each of the groups respectively, as shown in the diagram below. The DSI and BYTE RCGs serve as bypass clocks. We create a new set of ops clk_rcg_bypass2_ops, which are like the regular bypass ops, but don't take in a freq table, since the DSI driver using these clocks is parent-able. The PIXEL RCG needs to derive the required pixel clock using dsixpll. It parses a m/n frac table to retrieve the correct clock. The ESC RCG doesn't have a frac M/N block, it can just apply a pre- divider. Its ops simply check if the required clock rate can be achieved by the pre-divider. +-------------------+ | |---dsixpllbyte---o---> To byte RCG | | | (sets parent rate) | | | | | | | DSI 1/2 PLL | | | | o---> To esc RCG | | (doesn't set parent rate) | | | |----dsixpll-----o---> To dsi RCG +-------------------+ | (sets parent rate) ( x = 1, 2 ) | | o---> To pixel rcg (doesn't set parent rate) Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: xgene: Remove unused setup.h includeStephen Boyd2015-10-161-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This include doesn't look to be used, and compiling this file on arm64 still works, so remove it. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: Allow drivers to build if COMPILE_TEST is enabledJavier Martinez Canillas2015-10-163-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These drivers only have runtime but no build time dependencies so can be built for testing purposes if the Kconfig COMPILE_TEST option is enabled. This is useful to have more build coverage and make sure that drivers are not affected by changes that could cause build regressions. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Acked-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: Make clk input parameter of __clk_get_name() constGeert Uytterhoeven2015-10-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When calling __clk_get_name() on a const clock: warning: passing argument 1 of '__clk_get_name' discards 'const' qualifier from pointer target type include/linux/clk-provider.h:613:13: note: expected 'struct clk *' but argument is of type 'const struct clk *' __clk_get_name() does not modify the passed clock, hence make it const. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: shmobile: mstp: Drop bogus closing parenthesis in error messageGeert Uytterhoeven2015-10-161-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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