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| | * clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driverIcenowy Zheng2017-03-063-9/+323
| | * clk: sunxi-ng: gate: Support common pre-dividersChen-Yu Tsai2017-03-061-0/+47
| * | Merge branch 'clk-fixes' into clk-nextStephen Boyd2017-04-174-0/+74
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| * | | clk: cs2000: use existing priv_to_dev() to getting struct deviceKuninori Morimoto2017-04-121-5/+3
| * | | Merge tag 'meson-clk-for-4.12' of git://github.com/BayLibre/clk-meson into cl...Michael Turquette2017-04-126-13/+322
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| | * | | clk: meson: mpll: use 64bit math in rate_from_paramsMartin Blumenstingl2017-04-071-1/+1
| | * | | clk: meson: mpll: fix division by zero in rate_from_paramsMartin Blumenstingl2017-04-071-11/+15
| | * | | clk: meson: gxbb: add cts_i958 clockJerome Brunet2017-04-072-1/+23
| | * | | clk: meson: gxbb: add cts_mclk_i958Jerome Brunet2017-04-072-1/+56
| | * | | clk: meson: gxbb: add cts_amclkJerome Brunet2017-04-072-1/+71
| | * | | clk: meson: add audio clock divider supportJerome Brunet2017-04-073-1/+155
| | * | | clk: meson: gxbb: protect against holes in the onecell_data arrayJerome Brunet2017-04-071-0/+4
| * | | | Merge tag 'amlogic-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/khil...Michael Turquette2017-04-127-55/+854
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| | * | | Merge branch 'v4.12/clk-drivers' into v4.12/clkKevin Hilman2017-04-047-48/+840
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| | | * | | clk: meson-gxbb: Add GXL/GXM GP0 VariantNeil Armstrong2017-04-042-28/+275
| | | * | | clk: meson-gxbb: Add GP0 PLL init parametersNeil Armstrong2017-04-041-0/+13
| | | * | | clk: meson: Add support for parameters for specific PLLsNeil Armstrong2017-04-042-2/+74
| | | * | | clk: meson-gxbb: Add MALI clocksNeil Armstrong2017-04-041-0/+139
| | | * | | clk: meson: mpll: correct N2 maximum valueJerome Brunet2017-03-271-1/+1
| | | * | | clk: meson8b: add the mplls clocks 0, 1 and 2Jerome Brunet2017-03-272-1/+122
| | | * | | clk: meson: gxbb: mpll: use rw operationJerome Brunet2017-03-271-3/+3
| | | * | | clk: meson: mpll: add rw operationJerome Brunet2017-03-273-6/+180
| | | * | | clk: gxbb: put dividers and muxes in tablesJerome Brunet2017-03-271-8/+20
| | | * | | clk: meson8b: put dividers and muxes in tablesJerome Brunet2017-03-271-4/+18
| | | * | | clk: meson: add missing const qualifiers on gate arraysJerome Brunet2017-03-272-2/+2
| | | * | | clk: meson: fix SET_PARM macroJerome Brunet2017-03-271-1/+1
| * | | | | clk: aggregate return codes of notify chainsPeter De Schrijver2017-04-121-0/+2
| * | | | | clk: add clk_possible_parents debugfs filePeter De Schrijver2017-04-121-0/+32
| * | | | | clk: imx: correct uart4_serial clock name in driver for i.MX6ULRobin van der Gracht2017-04-121-1/+1
| * | | | | clk: zte: Mark pll config tables as constStephen Boyd2017-04-121-2/+2
| * | | | | clk: zte: add pll_vga clock for zx296718Shawn Guo2017-04-121-0/+24
| * | | | | clk: zte: pd_bit is not 0 on zx296718Shawn Guo2017-04-122-2/+16
| * | | | | clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocksShawn Guo2017-04-121-3/+3
| * | | | | clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clockRobin van der Gracht2017-04-121-4/+5
| * | | | | Merge tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/g...Michael Turquette2017-04-1214-253/+699
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| | * | | | | clk: tegra: Don't reset PLL-CX if it is already enabledJon Hunter2017-04-041-4/+4
| | * | | | | clk: tegra: Add missing Tegra210 clocksPeter De Schrijver2017-04-043-0/+19
| | * | | | | clk: tegra: Propagate clk_out_x rate to parentAlex Frid2017-04-041-2/+4
| | * | | | | clk: tegra: Fix build warnings on Tegra20/Tegra30Thierry Reding2017-03-202-2/+2
| | * | | | | clk: tegra: Mark TEGRA210_CLK_DBGAPB as always onPeter De Schrijver2017-03-201-0/+2
| | * | | | | clk: tegra: Add SATA seq input controlPeter De Schrijver2017-03-201-0/+25
| | * | | | | clk: tegra: Add Tegra210 special resetsPeter De Schrijver2017-03-201-0/+85
| | * | | | | clk: tegra: Rework pll_uPeter De Schrijver2017-03-202-197/+272
| | * | | | | clk: tegra: Implement reset control resetMikko Perttunen2017-03-201-0/+16
| | * | | | | clk: tegra: Fix disable unused for clocks sharing enable bitPeter De Schrijver2017-03-201-0/+3
| | * | | | | clk: tegra: Handle UTMIPLL IDDQPeter De Schrijver2017-03-201-0/+26
| | * | | | | clk: tegra: Add aclkPeter De Schrijver2017-03-201-0/+10
| | * | | | | clk: tegra: Add super clock mux/dividerPeter De Schrijver2017-03-202-5/+89
| | * | | | | clk: tegra: Define Tegra210 DMIC clocksPeter De Schrijver2017-03-203-1/+28
| | * | | | | clk: tegra: Fix constness for peripheral clocksPeter De Schrijver2017-03-202-4/+4
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