| Commit message (Collapse) | Author | Age | Files | Lines |
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Change the types here to unsigned int instead of int and update
the checks for == 0 instead < 1 to be more explicit about what's
going on now that of_clk_get_parent_count() has changed return
types.
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The return type of of_clk_get_parent_count() is an unsigned int
now, so let's update the code here to be more explicit about the
range of values we can test for.
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The checks for < 0 are impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the types.
Cc: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The checks for < 1 can be simplified now that
of_clk_get_parent_count() returns an unsigned int. Update the
code to reflect the int to unsigned int change.
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: <uclinux-h8-devel@lists.sourceforge.jp>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The check for < 0 is impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the type here.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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These checks for < 0 are impossible now that
of_clk_get_parent_count() returns an unsigned int. Change the
checks for == 0 and update the type.
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Russell King recently pointed out a bug in the clk-gpio code
where it fails to register the clk if of_clk_get_parent_count()
returns an error because the "clocks" property isn't present in
the DT node. If we're trying to count parents from DT we'd like
to know the count, not if there is a "clocks" property or not.
Furthermore, some drivers are assigning the return value to their
clk_init_data::num_parents member which is unsigned, leading to
potentially large numbers of parents when the property isn't
present.
Let's change the API to return an unsigned int instead of an int.
All the callers just want to know the count anyway, and this
avoids the bug that was in the clk-gpio driver.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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of_clk_init() uses for_each_matching_node_and_match() to find clock
providers, which returns all matching device nodes, whether they are
enabled or not. Hence clock providers that are disabled explicitly in DT
using e.g.
"status = "disabled";
are still activated.
Add a check to ignore device nodes that are not enabled, like
of_irq_init() does.
Reported-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Let's compare the degrees from clk_set_rate with
clk->core->phase. If the requested degrees is already
there, skip the following steps.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
[sboyd@codeaurora.org: s/drgrees/degrees/ in commit text]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Added missing CTRL and DIV clock register definitions for:
PCM, SLIM, TCNT, TEC, TD0, TD1
Register information taken from:
https://rawgit.com/msperl/rpi-registers/master/rpi-registers.html#CM
which extracted the information from the header files shared by
Broadcom/rpi foundation in this file:
http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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As of 9b5ba0df4ea4 ("ARM: shmobile: Introduce ARCH_RENESAS") all platforms
that use Renesas clock drivers now select ARCH_RENESAS. As it is present in
drivers/clk/Makefile ARCH_SHMOBILE_MULTI may now be removed.
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Pull Samsung clk driver changes from Sylwester Nawrocki:
Mostly correction of errors in the exynos5433 SoC
clocks definition, dropping read-only registers
from the suspend/resume register save/restore list
and exposition of two clocks required for the
exynos5433 HDMI subsystem operation.
* tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks
clk: samsung: exynos5433: Fix mout_aclk_cam1*_user clocks definition
clk: samsung: exynos5433: Drop RO registers from the save/restore lists
clk: samsung: exynos5433: Fix definitions of SCLK ISP SENSOR0 clocks
clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocks
clk: samsung: exynos5433: Fix typos in *_ISP_MPWM clock names
clk/samsung: exynos5433: add pclk_decon clock
clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks
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This fixes register assignment in the CLK_PCLK_SMMU_GSCL{1,2}
clocks definition.
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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Control bits for the ACLK_CAM1_552_USER and ACLK_CAM1_400_USER
mux clocks are in MUX_SEL_CAM10, not MUX_SEL_CAM01 register.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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Restoring read-only registers is of not much effect, drop them
from the respective lists.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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This fixes bit field offsets in the CMU_TOP CLK_DIV_SCLK_ISP_SENSOR_{A,B}
clock definitions.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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This corrects assignment of bit offsets of the MUX_SEL_CAM04 register
to the respective mux clocks.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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This fixes "MPWM" -> "WPWM" typo in 3 *ISP_MWPM clock definitions.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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This undocumented gate clock is used by DECON IP.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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HDMI driver must re-parent respective muxes during HDMI-PHY on/off
to HDMI-PHY output clocks. To reference those clocks their
definitions should be added.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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The core clock does not depend on corediv, so enabling corediv
based on the clock is not really correct. Move the corediv
config option from the clock driver Kconfig to the mvebu Kconfig
so that it can be enabled by the MACH option instead.
This also enables corediv on Armada 375 and 38X, which was
previously missing.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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There is no corediv clock on Armada XP, so this is unnecessary.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Despite care take to allocate clocks state containers the
SP810 driver actually just supports creating one instance:
all clocks registered for every instance will end up with the
exact same name and __clk_init() will fail.
Rename the timclken<0> .. timclken<n> to sp810_<instance>_<n>
so every clock on every instance gets a unique name.
This is necessary for the RealView PBA8 which has two SP810
blocks: the second block will not register its clocks unless
every clock on every instance is unique and results in boot
logs like this:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at ../drivers/clk/versatile/clk-sp810.c:137
clk_sp810_of_setup+0x110/0x154()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted
4.5.0-rc2-00030-g352718fc39f6-dirty #225
Hardware name: ARM RealView Machine (Device Tree Support)
[<c00167f8>] (unwind_backtrace) from [<c0013204>]
(show_stack+0x10/0x14)
[<c0013204>] (show_stack) from [<c01a049c>]
(dump_stack+0x84/0x9c)
[<c01a049c>] (dump_stack) from [<c0024990>]
(warn_slowpath_common+0x74/0xb0)
[<c0024990>] (warn_slowpath_common) from [<c0024a68>]
(warn_slowpath_null+0x1c/0x24)
[<c0024a68>] (warn_slowpath_null) from [<c051eb44>]
(clk_sp810_of_setup+0x110/0x154)
[<c051eb44>] (clk_sp810_of_setup) from [<c051e3a4>]
(of_clk_init+0x12c/0x1c8)
[<c051e3a4>] (of_clk_init) from [<c0504714>]
(time_init+0x20/0x2c)
[<c0504714>] (time_init) from [<c0501b18>]
(start_kernel+0x244/0x3c4)
[<c0501b18>] (start_kernel) from [<7000807c>] (0x7000807c)
---[ end trace cb88537fdc8fa200 ]---
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Fixes: 6e973d2c4385 "clk: vexpress: Add separate SP810 driver"
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This config was used for the ARM port so that it could use a
machine specific clkdev.h include, but those are all gone now.
The MIPS architecture is the last user, and from what I can tell
it doesn't actually use it anyway, so let's remove the config all
together.
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Joshua Henderson <joshua.henderson@microchip.com>
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* clk-ipq4019:
clk: qcom: Add IPQ4019 Global Clock Controller support
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This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Pradeep Banavathi <pradeepb@codeaurora.org>
Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
[sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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We forgot to free this clock when we return early in this code.
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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We were not checking the return from devm_add_action() which can fail.
Start using the helper devm_add_action_or_reset() and return directly
as we know that the cleanup has been done by this helper.
Signed-off-by: Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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__clk_init() was renamed to __clk_core_init() but these comments
weren't updated.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This reverts commit 858d5881564026cbc4e6f5e25ae878a27df5d4c9.
Joachim reports that this commit breaks lpc18xx boot. This is
because the hardware has circular clk topology where PLLs can
feed into dividers and the same dividers can feed into the PLLs.
The hardware is designed this way so that you can choose to put
the divider before the PLL or after the PLL depending on what you
configure to be the parent of the divider and what you configure
to be the parent of the PLL.
So let's drop this patch for now because we have hardware that
actually has loops. A future patch could check for circular
parents when we change parents and fail the switch, but that's
probably best left to some debugging Kconfig option so that we
don't suffer the sanity checking cost all the time.
Reported-by: Joachim Eastwood <manabian@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
have multiple parents. Fix up the __socfpga_periph_init() to call
of_clk_parent_fill() that will return the appropriate number of parents.
Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
function.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Convert DPLL support code to use clk_hw pointers for reference and bypass
clocks. This allows us to use clk_hw_* APIs for accessing any required
parameters for these clocks, avoiding some locking problems at least with
DPLL enable code; this used clk_get_rate which uses mutex but isn't
good under clk_enable / clk_disable.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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* clk-fixes:
clk: ti: omap3+: dpll: use non-locking version of clk_get_rate
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This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
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Add the "intc-ex" clock to the r8a7795 CPG MSSR driver.
According to information from the hardware team the INTC-EX
parent clock is CP. The next data sheet version will include
this information.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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This patch adds SD[0..3] clock divider support for R-Car Gen3 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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* clk-fixes:
clk: gpio: Really allow an optional clock= DT property
Revert "clk: qcom: Specify LE device endianness"
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Export symbol of_clk_get_from_provider so it can be used in
loadable kernel modules
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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We were rolling this ourselves, but clk-divider can do it now.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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Our dividers weren't being set successfully because CM_PASSWORD wasn't
included in the register write. It looks easier to just compute the
divider to write ourselves than to update clk-divider for the ability
to OR in some arbitrary bits on write.
Fixes about half of the video modes on my HDMI monitor (everything
except 720x400).
Cc: stable@vger.kernel.org
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Introduction of a factor type and a variant containing a gate
to be able to also declare factor clocks in their correct
place in the clock tree instead of having to register factor
clocks in the init callback separately. And as always some more
clock-ids and non-regression fixes for mistakes introduced in
past kernel releases.
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Clean up the init code and move the creation of factor clocks to the
appropriate positions coming from the clock architecture diagrams.
This also unifies the artificial separation of the hclk_vcodec etc clocks
again.
We do keep the separate definition of some watchdog and usb480m pseudo
clocks for now, as they're not real factor clocks from the clock-tree
but placeholders for fixes to come (usb480m gets supplied by the
missing driver for the new usbphy type and the watchdog-gate is sitting
somewhere else together which we cannot model currently).
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add a clock type for fixed factor clocks. This allows us to define fixed
factor clocks where they appear in the clock hierarchy instead of in the
init function.
The additional factor_gate type, finally allows us to model some last
parts of the clock tree correctly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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hclk_vcodec is a child of aclk_vcodec with the fixed factor clock
hclk_vcodec_pre in between and not a child of hclk_disp_pre.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add free memeory if rockchip_clk_register_branch fails.
Fixes: a245fecbb806 ("clk: rockchip: add basic infrastructure...")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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