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path: root/drivers/clk
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* clk: fixed: Add comment to clk_fixed_set_rateDaniel Thompson2015-06-101-1/+7
| | | | | | | | | | | | | Currently it is not made explicit why clk_fixed_set_rate() can ignore its arguments and unconditionally return success. Add a comment to explain this. We also mark the clk_ops table const since it should never be modified at runtime. Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: cdce925: Fix printk size_t warningStephen Boyd2015-06-101-1/+1
| | | | | | | | | drivers/clk/clk-cdce925.c:550: warning: format ‘%u’ expects type ‘unsigned int’, but argument 6 has type ‘size_t’ Cc: Mike Looijmans <mike.looijmans@topic.nl> Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: socfpga: remove a stray tabDan Carpenter2015-06-091-1/+1
| | | | | | | | This line was indented too far. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: exynos5433: Add CLK_IGNORE_UNUSED flag to clocks for SMCJonghwa Lee2015-06-091-18/+18
| | | | | | | | | | This patch adds 'CLK_IGNORE_UNUSED' flag to clocks which is required for operation of secure monitor call (smc). System will hang when it executes 'smc' with one of those clock is gated. All related clocks must be enabled. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: exynos5433: Add clock flag to support the DVFS of GPUJoonyoung Shim2015-06-091-9/+9
| | | | | | | | | | | | | This patch adds the CLK_SET_RATE_PARENT flag for 'aclk_g3d' clock and parent clocks becuase 'aclk_g3d' is used to change GPU frequency for DVFS (Dynamic Voltage Frequency Scaling) feature and adds CLK_IGNORE_UNUSED flags to 'aclk_asyncapbs_g3d'/'aclk_asyncapbm_g3d' clocks to access the SFR of the MALI device. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> [cw00.choi: Add patch description and add CLK_SET_RATE_PARENT to 'aclk_g3d' clk] Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: exynos5433: Add DIV_CPIF to the list of stored registers on suspendHyungwon Hwang2015-06-091-0/+1
| | | | | | | | | | This DIV_CPIF register must be stored when the system is suspended, and must be restored on system resume. This patch adds the register to the list of restored registers. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: exynos5433: Add CLK_SET_RATE_PARENT to support DVFS for big.LITTLE coreChanwoo Choi2015-06-091-14/+12
| | | | | | | | | | | This patch adds CLK_SET_RATE_PARENT flag to support DVFS of Cortex-{A53|A57} core (big.LITTLE core) because 'sclk_{apollo|atlas}' leaf clock is used to change the CPU frequency of Cortex-{A53|A57} core in arm_big_little.c driver. - 'apollo' word means the LITTLE core (Cortex-A53 core) in Exynos5433 TRM. - 'atlas' word means the big core (Cortex-A57 core) in Exynos5433 TRM. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: socfpga: make use of of_clk_parent_fill helper functionDinh Nguyen2015-06-052-11/+2
| | | | | | | Use of_clk_parent_fill to fill in the parent clock's array. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: of: helper for filling parent clock array and return num of parentsDinh Nguyen2015-06-051-0/+21
| | | | | | | | | | | | | | | | Sprinkled all through the platform clock drivers are code like this to fill the clock parent array: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); The of_clk_parent_fill() will do the same as the code above, and while at it, return the number of parents as well since the logic of the function is to the walk the clock node to look for the parent. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> [sboyd@codeaurora.org: Fixed kernel-doc] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge branch 'clk-meson8b' into clk-nextStephen Boyd2015-06-057-0/+1101
|\ | | | | | | | | | | | | * clk-meson8b: clk: meson8b: Add support for Meson8b clocks clk: meson: Document bindings for Meson8b clock controller clk: meson: Add support for Meson clock controller
| * clk: meson8b: Add support for Meson8b clocksCarlo Caione2015-06-052-0/+197
| | | | | | | | | | | | | | | | This patch adds support for the basic clocks found on the Amlogic Meson8b SoCs. Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: meson: Add support for Meson clock controllerCarlo Caione2015-06-056-0/+904
| | | | | | | | | | | | | | | | | | | | | | | | This patchset adds the infrastructure for registering and managing the core clocks found on Amlogic MesonX SoCs. In particular: - PLLs - CPU clock - Fixed rate clocks, fixed factor clocks, ... Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: make several parent names constUwe Kleine-König2015-06-0417-146/+154
| | | | | | | | | | | | | | | | | | | | | | Since commit 2893c379461a ("clk: make strings in parent name arrays const") the name of parent clocks can be const. So add more const in several clock drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: mediatek: Fix apmixedsys clock registrationJames Liao2015-06-042-2/+2
| | | | | | | | | | | | | | | | | | | | The size of clk_data should be the same as CLK_APMIXED_NR_CLK instead of ARRAY_SIZE(plls). CLK_APMIXED_* is numbered from 1, so CLK_APMIXED_NR_CLK will be greater than ARRAY_SIZE(plls). Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: ti: Use of_clk_get_parent_count() instead of open codingGeert Uytterhoeven2015-06-041-1/+1
| | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: st: Use of_clk_get_parent_count() instead of open codingGeert Uytterhoeven2015-06-042-2/+2
| | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: at91: Use of_clk_get_parent_count() instead of open codingGeert Uytterhoeven2015-06-046-7/+7
| | | | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: pistachio: Add sanity checks on PLL configurationKevin Cernekee2015-06-041-4/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When setting the PLL rates, check that: - VCO is within range - PFD is within range - PLL is disabled when postdiv is changed - postdiv2 <= postdiv1 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Kevin Cernekee <cernekee@chromium.org> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: pistachio: Lock the PLL when enabled upon rate changeEzequiel Garcia2015-06-041-18/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when the rate is changed, the driver makes sure the PLL is enabled before doing so. This is done because the PLL cannot be locked while disabled. Once locked, the drivers returns the PLL to its previous enable/disable state. This is a bit cumbersome, and can be simplified. This commit reworks the .set_rate() functions for the integer and fractional PLLs. Upon rate change, the PLL is now locked only if it's already enabled. Also, the driver locks the PLL on .enable(). This makes sure the PLL is locked when enabled, and not locked when disabled. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: pistachio: Add a pll_lock() helper for clarityEzequiel Garcia2015-06-041-4/+8
| | | | | | | | | | | | | | | | | | This commit adds a pll_lock() helper making the code more readable. Cosmetic change only, no functionality changes. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: mmp: add timer clock for pxa168/mmp2/pxa910Chao Xie2015-06-043-0/+24
| | | | | | | | | | | | | | | | Timer has external fast clock, and it is a mux clock. Add the timer clock type for timer driver. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: mmp: Fix the wrong factor table for uart PLLChao Xie2015-06-042-6/+2
| | | | | | | | | | | | | | | | | | | | The suggested value in the mmp2 manual is wrong. There are only 13 bits for numerator, but some suggested value has 14 bits. Fix the factor tabled and remove the unused items. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: mmp: add fixed clock UBS_PLL for pxa910/pxa168Chao Xie2015-06-042-0/+2
| | | | | | | | | | | | | | USB will drive clock from USB_PLL. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge branch 'clk-next-hi6220' into clk-nextMichael Turquette2015-06-038-15/+507
|\ \ | | | | | | | | | | | | Conflicts: drivers/clk/Kconfig
| * | clk: hi6220: Clock driver support for Hisilicon hi6220 SoCBintian Wang2015-06-038-4/+496
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock drivers for hi6220 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. We add one divider clock for hi6220 because the divider in hi6220 also has a mask bit but it doesnot obey the rule defined by flag "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by left shift fixed bits (e.g. 16 bits), so we add this divider clock to handle it. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by: Will Deacon <will.deacon@arm.com> Tested-by: Tyler Baker <tyler.baker@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | clk: hisilicon: Remove __init for marking function prototypesBintian Wang2015-06-031-11/+11
| |/ | | | | | | | | | | | | | | | | | | | | | | __init markings on function prototypes are useless, so remove them. Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Tested-by: Will Deacon <will.deacon@arm.com> Tested-by: Tyler Baker <tyler.baker@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | Add TI CDCE925 I2C controlled clock synthesizer driverMike Looijmans2015-06-033-0/+767
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver supports the TI CDCE925 programmable clock synthesizer. The chip contains two PLLs with spread-spectrum clocking support and five output dividers. The driver only supports the following setup, and uses a fixed setting for the output muxes: Y1 is derived from the input clock Y2 and Y3 derive from PLL1 Y4 and Y5 derive from PLL2 Given a target output frequency, the driver will set the PLL and divider to best approximate the desired output. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: mvebu: add missing CESA gate clkBoris Brezillon2015-06-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | Even if not documented in the datasheet, the Armada 370 SoC can actually gate the CESA (crypto engine) clock. Add an entry in the gating_desc table to be able to reference the CESA gateclk in the crypto node. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: socfpga: add a clock driver for the Arria 10 platformDinh Nguyen2015-05-216-1/+469
| | | | | | | | | | | | | | | | | | The clocks on the Arria 10 platform is a bit different than the Cyclone/Arria 5 platform that it should just have it's own driver. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: socfpga: update clk.h so for Arria10 platform to useDinh Nguyen2015-05-212-5/+5
| | | | | | | | | | | | | | | | | | There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver can use. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: clk-conf: Fix typo in commentShailendra Verma2015-05-211-1/+1
| | | | | | | | | | Signed-off-by: Shailendra Verma <shailendra.capricorn@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: samsung: Fix typo in panic logShailendra Verma2015-05-211-1/+1
| | | | | | | | | | Signed-off-by: Shailendra Verma <shailendra.capricorn@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: cdce706: Add missing of_clk_del_provider call in cdce706_removeAxel Lin2015-05-211-0/+1
| | | | | | | | | | | | | | | | Remove a previously registered clock provider when unload the module. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: Fix typo in clk_register() commentShailendra Verma2015-05-201-1/+1
| | | | | | | | | | Signed-off-by: Shailendra Verma <shailendra.capricorn@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: sirf: add CSR atlas7 clk and reset supportZhiwu Song2015-05-202-1/+1633
| | | | | | | | | | | | | | | | | | | | | | | | | | the hardware node includes both clock and reset support, so it is named as "car". this patch implements Flexible clocks(mux, divider, gate), Selectable clock(mux, divider, gate), root clock(gate),leaf clock(gate), others. it also implements the reset controller functionality. Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Guo Zeng <Guo.Zeng@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: mediatek: Initialize clk_init_dataRicky Liang2015-05-192-2/+2
| | | | | | | | | | | | | | | | | | | | | | The variable init (struct clk_init_data) is allocated on the stack. We weren't initializing the .flags field, so it contains random junk, which can cause all kinds of interesting issues when the flags are parsed by clk_register. Signed-off-by: Ricky Liang <jcliang@chromium.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: mmp: add PXA1928 clock supportRob Herring2015-05-152-0/+267
| | | | | | | | | | | | | | | | | | | | | | | | | | Add initial clock support for Marvell PXA1928. The PXA1928 is a mobile SOC and is similar to other MMP/PXA series of SOCs, so a lot of the existing infrastructure is reused here. Currently the PLLs are just fixed clocks, and not all leaf clocks are implemented. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: Show correct information when fail to set clock rateChanwoo Choi2015-05-151-2/+3
| | | | | | | | | | | | | | | | | | | | | | This patch shows the correct information for debugging when fail to set clock rate because original error message shows the error value instead of current clock rate. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: Kconfig: Move bcm Kconfig into clk menuStephen Boyd2015-05-141-1/+1
| | | | | | | | | | | | | | | | | | | | Having this Kconfig sourced outside the clk menu means the option is under the "Device Drivers" menu instead of the "Common Clock Framework" menu. Move it so that the bcm clock config options are in the right place. Cc: Alex Elder <elder@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: u300: Silence sparse warningsStephen Boyd2015-05-141-0/+1
| | | | | | | | | | | | | | drivers/clk/clk-u300.c:1175:13: warning: symbol 'u300_clk_init' was not declared. Should it be static? Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: moxart: Silence sparse warningsStephen Boyd2015-05-141-2/+2
| | | | | | | | | | | | | | | | drivers/clk/clk-moxart.c:18:13: warning: symbol 'moxart_of_pll_clk_init' was not declared. Should it be static? drivers/clk/clk-moxart.c:56:13: warning: symbol 'moxart_of_apb_clk_init' was not declared. Should it be static? Cc: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: xgene: Silence sparse warningsStephen Boyd2015-05-141-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | drivers/clk/clk-xgene.c:77:43: warning: incorrect type in argument 1 (different address spaces) drivers/clk/clk-xgene.c:77:43: expected void *csr drivers/clk/clk-xgene.c:77:43: got void [noderef] <asn:2>* ... drivers/clk/clk-xgene.c: In function ‘xgene_clk_enable’: drivers/clk/clk-xgene.c:237:3: warning: format ‘%LX’ expects argument of type ‘long long unsigned int’, but argument 4 has type ‘phys_addr_t’ [-Wformat] drivers/clk/clk-xgene.c:248:3: warning: format ‘%LX’ expects argument of type ‘long long unsigned int’, but argument 4 has type ‘phys_addr_t’ [-Wformat] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: mmp: Silence sparse warningsStephen Boyd2015-05-142-2/+2
| | | | | | | | | | | | | | | | drivers/clk/mmp/clk-apbc.c:118:16: warning: symbol 'clk_apbc_ops' was not declared. Should it be static? drivers/clk/mmp/clk-apmu.c:64:16: warning: symbol 'clk_apmu_ops' was not declared. Should it be static? Cc: Chao Xie <chao.xie@marvell.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: socfpga: Silence sparse warningStephen Boyd2015-05-141-1/+1
| | | | | | | | | | | | | | drivers/clk/socfpga/clk-periph.c:79:39: warning: Using plain integer as NULL pointer Cc: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: versatile: Silence sparse warningsStephen Boyd2015-05-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | drivers/clk/versatile/clk-sp810.c:159:29: error: incompatible types for operation (<=) drivers/clk/versatile/clk-sp810.c:159:29: left side has type char const *<noident> drivers/clk/versatile/clk-sp810.c:159:29: right side has type int drivers/clk/versatile/clk-sp810.c:159:53: error: incompatible types for operation (<=) drivers/clk/versatile/clk-sp810.c:159:53: left side has type char const *<noident> drivers/clk/versatile/clk-sp810.c:159:53: right side has type int drivers/clk/versatile/clk-sp810.c:138:13: warning: symbol 'clk_sp810_of_setup' was not declared. Should it be static? Acked: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: ti: Silence sparse warningsStephen Boyd2015-05-144-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/clk/ti/clk.c:125:31: warning: incorrect type in return expression (different address spaces) drivers/clk/ti/clk.c:125:31: expected void [noderef] <asn:2>* drivers/clk/ti/clk.c:125:31: got void * drivers/clk/ti/clk.c:132:31: warning: incorrect type in return expression (different address spaces) drivers/clk/ti/clk.c:132:31: expected void [noderef] <asn:2>* drivers/clk/ti/clk.c:132:31: got void * drivers/clk/ti/dpll.c:180:14: warning: symbol '_get_reg' was not declared. Should it be static? drivers/clk/ti/fapll.c:624:32: warning: Using plain integer as NULL pointer drivers/clk/ti/fapll.c:625:31: warning: Using plain integer as NULL pointer drivers/clk/ti/fapll.c:630:40: warning: Using plain integer as NULL pointer drivers/clk/ti/clk-dra7-atl.c:158:22: warning: symbol 'atl_clk_ops' was not declared. Should it be static? drivers/clk/ti/clk-dra7-atl.c:170:39: warning: Using plain integer as NULL pointer Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: st: Silence sparse warningsStephen Boyd2015-05-144-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/clk/st/clkgen-mux.c:134:4: warning: symbol 'clkgena_divmux_get_parent' was not declared. Should it be static? drivers/clk/st/clkgen-mux.c:171:15: warning: symbol 'clkgena_divmux_recalc_rate' was not declared. Should it be static? drivers/clk/st/clkgen-mux.c:218:12: warning: symbol 'clk_register_genamux' was not declared. Should it be static? drivers/clk/st/clkgen-mux.c:388:13: warning: symbol 'st_of_clkgena_divmux_setup' was not declared. Should it be static? drivers/clk/st/clkgen-mux.c:488:13: warning: symbol 'st_of_clkgena_prediv_setup' was not declared. Should it be static? drivers/clk/st/clkgen-mux.c:625:13: warning: symbol 'st_of_clkgen_mux_setup' was not declared. Should it be static? drivers/clk/st/clkgen-mux.c:702:13: warning: symbol 'st_of_clkgen_vcc_setup' was not declared. Should it be static? drivers/clk/st/clkgen-pll.c:273:15: warning: symbol 'recalc_stm_pll800c65' was not declared. Should it be static? drivers/clk/st/clkgen-pll.c:300:15: warning: symbol 'recalc_stm_pll1600c65' was not declared. Should it be static? drivers/clk/st/clkgen-pll.c:324:15: warning: symbol 'recalc_stm_pll3200c32' was not declared. Should it be static? drivers/clk/st/clkgen-pll.c:346:15: warning: symbol 'recalc_stm_pll1200c32' was not declared. Should it be static? drivers/clk/st/clkgen-pll.c:565:19: warning: incorrect type in assignment (different address spaces) drivers/clk/st/clkgen-pll.c:565:19: expected void [noderef] <asn:2>*reg drivers/clk/st/clkgen-pll.c:565:19: got void * drivers/clk/st/clkgen-pll.c:576:18: warning: incorrect type in assignment (different address spaces) drivers/clk/st/clkgen-pll.c:576:18: expected void [noderef] <asn:2>*reg drivers/clk/st/clkgen-pll.c:576:18: got void * drivers/clk/st/clkgen-pll.c:693:53: warning: incorrect type in argument 2 (different address spaces) drivers/clk/st/clkgen-pll.c:693:53: expected void *[noderef] <asn:2>reg drivers/clk/st/clkgen-pll.c:693:53: got void [noderef] <asn:2>*[assigned] pll_base drivers/clk/st/clkgen-fsyn.c:495:5: warning: symbol 'clk_fs660c32_vco_get_rate' was not declared. Should it be static? drivers/clk/st/clkgen-fsyn.c:522:5: warning: symbol 'clk_fs660c32_vco_get_params' was not declared. Should it be static? drivers/clk/st/clk-flexgen.c:119:15: warning: symbol 'flexgen_recalc_rate' was not declared. Should it be static? drivers/clk/st/clk-flexgen.c:177:12: warning: symbol 'clk_register_flexgen' was not declared. Should it be static? drivers/clk/st/clk-flexgen.c:263:13: warning: symbol 'st_of_flexgen_setup' was not declared. Should it be static? Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: socfpga: Silence sparse warningStephen Boyd2015-05-141-1/+1
| | | | | | | | | | | | | | drivers/clk/socfpga/clk-gate.c:227:40: warning: Using plain integer as NULL pointer Cc: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: sirf: Silence sparse warningsStephen Boyd2015-05-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | These are __iomem pointers. Mark them appropriately so we don't get sparse errors like drivers/clk/sirf/clk-common.c:60:16: warning: incorrect type in argument 1 (different address spaces) drivers/clk/sirf/clk-common.c:60:16: expected void const volatile [noderef] <asn:2>*addr drivers/clk/sirf/clk-common.c:60:16: got void * Cc: Barry Song <Baohua.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: emev2: Silence sparse warningsStephen Boyd2015-05-141-1/+1
| | | | | | | | | | | | | | | | | | drivers/clk/shmobile/clk-emev2.c:37:14: warning: symbol 'smu_base' was not declared. Should it be static? Cc: Takashi Yoshii <takasi-y@ops.dti.ne.jp> Cc: Magnus Damm <damm@opensource.se> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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