summaryrefslogtreecommitdiffstats
path: root/drivers/clk
Commit message (Expand)AuthorAgeFilesLines
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2018-06-09138-1156/+12576
|\
| * Merge branch 'clk-imx6ul' into clk-nextStephen Boyd2018-06-041-1/+1
| |\
| | * clk: imx6ul: fix periph clk2 clock mux selectionStefan Agner2018-05-041-1/+1
| | |
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| *-------. \ Merge branches 'clk-davinci-psc-da830', 'clk-renesas', 'clk-at91-recalc', 'cl...Stephen Boyd2018-06-0450-502/+1545
| |\ \ \ \ \ \
| | | | | | * | clk: meson: axg: let mpll clocks round closestJerome Brunet2018-05-211-0/+4
| | | | | | * | clk: meson: mpll: add round closest supportJerome Brunet2018-05-212-5/+22
| | | | | | * | clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICALMartin Blumenstingl2018-05-211-0/+7
| | | | | | * | clk: meson: use SPDX license identifiers consistentlyJerome Brunet2018-05-1813-238/+20
| | | | | | * | clk: meson: drop CLK_SET_RATE_PARENT flagYixun Lan2018-05-151-1/+1
| | | | | | * | clk: meson-axg: Add AO Clock and Reset controller driverQiufang Dai2018-05-154-1/+195
| | | | | | * | clk: meson: aoclk: refactor common code into dedicated fileYixun Lan2018-05-156-62/+160
| | | | | | * | clk: meson: migrate to devm_of_clk_add_hw_provider APIYixun Lan2018-05-151-1/+1
| | | | | | * | clk: meson: gxbb: add the video decoder clocksMaxime Jourdan2018-05-152-1/+119
| | | | | | * | clk: meson: meson8b: add support for the NAND clocksMartin Blumenstingl2018-05-152-1/+58
| | | | | | |/
| | | | | * | clk: davinci: Fix link errors when not all SoCs are enabledDavid Lechner2018-05-304-3/+50
| | | | | * | clk: davinci: psc: allow for dev == NULLDavid Lechner2018-05-305-18/+52
| | | | | * | clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLAREDavid Lechner2018-05-303-6/+21
| | | | | * | clk: davinci: pll: allow dev == NULLDavid Lechner2018-05-308-137/+235
| | | | | * | clk: davinci: psc-dm365: fix few clocksSekhar Nori2018-05-301-3/+16
| | | | | * | clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabledSekhar Nori2018-05-301-1/+1
| | | | | * | clk: davinci: psc-dm355: fix ASP0/1 clkdev lookupsDavid Lechner2018-05-301-2/+2
| | | | | * | clk: davinci: pll-dm355: fix SYSCLKn parent namesDavid Lechner2018-05-301-5/+5
| | | | | * | clk: davinci: pll-dm355: drop pll2_sysclk2David Lechner2018-05-301-4/+1
| | | | | |/
| | | | * | clk: at91: PLL recalc_rate() now using cached MUL and DIV valuesMarcin Ziemianowicz2018-05-151-12/+1
| | | | |/
| | | * | clk: renesas: cpg-mssr: Add support for R-Car E3Yoshihiro Shimoda2018-05-095-0/+302
| | | * | clk: renesas: rcar-gen2: Centralize quirks handlingGeert Uytterhoeven2018-04-161-4/+16
| | | * | clk: renesas: r8a77980: Correct parent clock of PCIEC0Geert Uytterhoeven2018-04-161-1/+1
| | | * | clk: renesas: r8a7794: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | * | clk: renesas: r8a7792: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | * | clk: renesas: r8a7791/r8a7793: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | * | clk: renesas: r8a7745: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | * | clk: renesas: r8a7743: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| | | * | clk: renesas: cpg-mssr: Add r8a77470 supportBiju Das2018-04-166-0/+254
| | | * | clk: renesas: r8a77965: Add MSIOF controller clocksTakeshi Kihara2018-04-161-0/+4
| | | |/
| | * | clk: davinci: psc-da830: fix USB0 48MHz PHY clock registrationSekhar Nori2018-05-151-1/+2
| | |/
| * | Merge branch 'clk-qcom-8996-halt' into clk-nextStephen Boyd2018-06-041-0/+6
| |\ \
| | * | clk: qcom: gcc-msm8996: Disable halt check on UFS clocksBjorn Andersson2018-06-011-0/+2
| | * | clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clkManu Gautam2018-06-011-0/+4
| * | | Merge branch 'clk-qcom-sdm845' into clk-nextStephen Boyd2018-06-0412-62/+4395
| |\ \ \
| | * | | clk: qcom: Export clk_fabia_pll_configure()Stephen Boyd2018-06-021-0/+1
| | * | | clk: qcom: Add video clock controller driver for SDM845Amit Nischal2018-06-013-0/+370
| | * | | clk: qcom: Add Global Clock controller (GCC) driver for SDM845Taniya Das2018-05-083-0/+3475
| | * | | clk: qcom: Configure the RCGs to a safe source as neededAmit Nischal2018-05-082-24/+155
| | |/ /
| | * | clk: qcom: Add support for BRANCH_HALT_SKIP flag for branch clocksAmit Nischal2018-05-082-2/+6
| | * | clk: qcom: Simplify gdsc status checking logicStephen Boyd2018-05-081-19/+37
| | * | clk: qcom: gdsc: Add support to poll CFG register to check GDSC stateAmit Nischal2018-05-012-16/+27
| | * | clk: qcom: gdsc: Add support to poll for higher timeout valueAmit Nischal2018-04-161-1/+1
| | * | clk: qcom: gdsc: Add support to reset AON and block reset logicAmit Nischal2018-04-162-3/+23
| | * | clk: qcom: Add support for controlling Fabia PLLAmit Nischal2018-03-192-8/+311
| | * | clk: qcom: Clear hardware clock control bit of RCGAmit Nischal2018-03-191-2/+3
OpenPOWER on IntegriCloud