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path: root/drivers/clk/ti/apll.c
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* clk: ti: move some public definitions to private headerTero Kristo2015-06-021-0/+2
| | | | | | | | | Several exported TI clock driver features are no longer needed outside the clock driver itself, thus move all of these to the driver private header file. Also, update some of the driver files to actually include this header. Signed-off-by: Tero Kristo <t-kristo@ti.com>
* clk: ti: fix ti_clk_get_reg_addr error handlingTero Kristo2015-03-241-2/+3
| | | | | | | | | | | | There is a case where NULL can be a valid return value for ti_clk_get_reg_addr, specifically the case where both the provider index and register offsets are zero. In this case, the current error checking against a NULL pointer will fail. Thus, change the API to return a ERR_PTR value in an error case, and change all the users of this API to check against IS_ERR instead. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Michael Turquette <mturquette@linaro.org>
* clk: ti: dra7: return error code in failure caseJulia Lawall2014-06-191-4/+2
| | | | | | | | | Add a returned error code in the MAX_APLL_WAIT_TRIES case. Remove the updating of the return variable r to 0 if MAX_APLL_WAIT_TRIES is not yet reached, because r is already 0 at this point. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* clk: ti: apll: not allocating enough dataDan Carpenter2014-06-191-1/+1
| | | | | | | | | There is a cut and paste bug here which will lead to memory corruption because we don't allocate enough data. Fixes: 4d008589e271 ('CLK: TI: APLL: add support for omap2 aplls') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* CLK: TI: APLL: add support for omap2 apllsTero Kristo2014-05-281-0/+181
| | | | | | | This patch adds support for omap2 type aplls, which have gating and autoidle functionality. Signed-off-by: Tero Kristo <t-kristo@ti.com>
* CLK: TI: DRA7: Add APLL supportJ Keerthy2014-01-171-0/+223
The patch adds support for DRA7 PCIe APLL. The APLL sources the optional functional clocks for PCIe module. APLL stands for Analog PLL. This is different when comapred with DPLL meaning Digital PLL, the phase detection is done using an analog circuit. Signed-off-by: J Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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