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* clk: tegra: Fix the misnaming of nvenc from msencRhyland Klein2016-02-021-1/+1
* clk: tegra: Fix naming of MISC registersRhyland Klein2016-02-021-18/+18
* clk: tegra: Remove improper flags for lock_enableRhyland Klein2016-01-251-28/+14
* clk: tegra: Fix divider on VI_I2CRhyland Klein2016-01-251-1/+1
* Merge tag 'asm-generic-for-linus' of git://git.kernel.org/pub/scm/linux/kerne...Linus Torvalds2016-01-201-2/+2
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| * tegra/clk-divider: fix wrong do_div() usageNicolas Pitre2015-11-161-2/+2
* | clk: tegra: Read correct IDDQ register in PLL_SS registrationBill Huang2015-12-171-4/+7
* | clk: tegra: Fix WARN_ON in PLL_RE registrationBill Huang2015-12-171-1/+2
* | clk: tegra: pll: Fix issues with rates for VCO PLLsAndrew Bresticker2015-12-171-4/+12
* | clk: tegra: Add support for Tegra210 clocksRhyland Klein2015-12-175-0/+2868
* | clk: tegra: Add Super Gen5 LogicBill Huang2015-12-172-13/+132
* | clk: tegra: pll: Add logic for SSBill Huang2015-12-172-1/+28
* | clk: tegra: pll: Add dyn_ramp callbackRhyland Klein2015-12-172-0/+11
* | clk: tegra: pll: Add Set_default logicBill Huang2015-12-172-11/+39
* | clk: tegra: pll: Adjust vco_min if SDM presentBill Huang2015-12-172-0/+32
* | clk: tegra: pll: Add support for PLLMB for Tegra210Rhyland Klein2015-12-172-5/+52
* | clk: tegra: pll: Add specialized logic for Tegra210Rhyland Klein2015-12-172-2/+346
* | clk: tegra: pll: Update PLLM handlingDanny Huang2015-11-203-51/+10
* | clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein2015-11-205-304/+379
* | clk: tegra: pll: Add code to handle if resets are supported by PLLBill Huang2015-11-202-0/+16
* | clk: tegra: pll: Add logic for out-of-table rates for T210Rhyland Klein2015-11-202-2/+35
* | clk: tegra: pll: Add logic for handling SDM dataRhyland Klein2015-11-202-2/+79
* | clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein2015-11-205-45/+55
* | clk: tegra: pll: Change misc_reg count from 3 to 6Bill Huang2015-11-201-1/+3
* | clk: tegra: pll: Update warning messageRhyland Klein2015-11-201-1/+2
* | clk: tegra: pll: Simplify clk_enable_pathRhyland Klein2015-11-201-54/+22
* | clk: tegra: pll: Add tegra_pll_wait_for_lock to clk headerRhyland Klein2015-11-202-0/+6
* | clk: tegra: periph: Add new periph clks and muxes for Tegra210Rhyland Klein2015-11-202-5/+434
* | clk: tegra: Constify pdiv-to-hw mappingsThierry Reding2015-11-206-15/+15
* | clk: tegra: Format tables consistentlyThierry Reding2015-11-184-652/+646
* | clk: tegra: Miscellaneous coding style cleanupsThierry Reding2015-11-185-25/+19
* | clk: tegra: Fix 26 MHz oscillator frequencyThierry Reding2015-11-183-3/+3
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* Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Michael Turquette2015-10-207-113/+163
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| * clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein2015-10-205-11/+56
| * clk: tegra: Update struct tegra_clk_pll_params kerneldocThierry Reding2015-10-201-3/+15
| * clk: tegra: Fix comments for structure definitionsRhyland Klein2015-10-201-37/+37
| * clk: tegra: dfll: Monitor code is DEBUG_FS onlyThierry Reding2015-10-201-50/+49
| * clk: tegra: Unlock top rates for Tegra124 DFLL clockMikko Perttunen2015-09-152-14/+8
* | clk: tegra: delete unneeded of_node_putJulia Lawall2015-10-121-3/+1
* | clk: tegra: dfll: Properly protect OPP listThierry Reding2015-09-161-1/+7
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* clk: tegra: Fix some static checker problemsStephen Boyd2015-08-252-7/+9
* Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd2015-08-2510-9/+2304
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| * clk: tegra: Add the DFLL as a possible parent of the cclk_g clockTuomas Tynkkynen2015-07-161-1/+3
| * clk: tegra: Save/restore CCLKG_BURST_POLICY on suspendTuomas Tynkkynen2015-07-161-0/+14
| * clk: tegra: Add Tegra124 DFLL clocksource platform driverTuomas Tynkkynen2015-07-164-4/+172
| * clk: tegra: Add DFLL DVCO reset control for Tegra124Paul Walmsley2015-07-161-0/+68
| * clk: tegra: Introduce ability for SoC-specific reset control callbacksMikko Perttunen2015-07-162-8/+34
| * clk: tegra: Add functions for parsing CVB tablesTuomas Tynkkynen2015-07-162-0/+207
| * clk: tegra: Add closed loop support for the DFLLTuomas Tynkkynen2015-07-161-3/+663
| * clk: tegra: Add library for the DFLL clock source (open-loop mode)Tuomas Tynkkynen2015-07-163-0/+1150
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