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* clk: tegra: Implement reset control resetMikko Perttunen2017-03-201-0/+16
| | | | | | | | | | For completeness, also implement this reset framework API for Tegra. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge tag 'tegra-for-4.7-clk' of ↵Stephen Boyd2016-05-021-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next Pull tegra clk driver changes from Thierry Reding: This set of changes contains a bunch of cleanups and minor fixes along with some new clocks, mainly on Tegra210, in preparation for supporting DisplayPort and HDMI 2.0. * tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: dfll: Reformat CVB frequency table clk: tegra: dfll: Properly clean up on failure and removal clk: tegra: dfll: Make code more comprehensible clk: tegra: dfll: Reference CVB table instead of copying data clk: tegra: dfll: Update kerneldoc clk: tegra: Fix PLL_U post divider and initial rate on Tegra30 clk: tegra: Initialize PLL_C to sane rate on Tegra30 clk: tegra: Fix pllre Tegra210 and add pll_re_out1 clk: tegra: Add sor_safe clock clk: tegra: dpaux and dpaux1 are fixed factor clocks clk: tegra: Add dpaux1 clock clk: tegra: Use correct parent for dpaux clock clk: tegra: Add fixed factor peripheral clock type clk: tegra: Special-case mipi-cal parent on Tegra114 clk: tegra: Remove trailing blank line clk: tegra: Constify peripheral clock registers clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
| * clk: tegra: Constify peripheral clock registersThierry Reding2016-04-281-2/+2
| | | | | | | | | | | | | | | | The peripheral clock registers are defined in static tables. These tables never need to be modified at runtime, so they can reside in read-only memory. Signed-off-by: Thierry Reding <treding@nvidia.com>
* | clk: tegra: Make reset_control_ops constPhilipp Zabel2016-03-291-1/+1
|/ | | | | | | The rst_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'tegra-for-4.3-clk' of ↵Stephen Boyd2015-08-251-8/+31
|\ | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk: tegra: Changes for v4.3-rc1 This contains the DFLL driver needed to implement CPU frequency scaling on Tegra.
| * clk: tegra: Introduce ability for SoC-specific reset control callbacksMikko Perttunen2015-07-161-8/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows SoC-specific CAR initialization routines to register their own reset_assert and reset_deassert callbacks with the common Tegra CAR code. If defined, the common code will call these callbacks when a reset control with number >= num_periph_banks * 32 is attempted to be asserted or deasserted respectively. Numbers greater than or equal to num_periph_banks * 32 are used to avoid clashes with low numbers that are automatically mapped to standard CAR reset lines. Each SoC with these special resets should specify the defined reset control numbers in a device tree header file. Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | clk: tegra: Properly include clk.hStephen Boyd2015-07-201-0/+1
|/ | | | | | | | | | | Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h in files that are using it. Also add in a clkdev.h include that was missing in a file using clkdev APIs. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: Add peripheral registers for bank YThierry Reding2015-04-101-0/+14
| | | | | | | | | | Tegra210 has an extra bank of peripheral clock registers. Add it to the generic peripheral clock code. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Register the proper number of resetsThierry Reding2015-04-101-1/+1
| | | | | | | | | | | | | | | | | The number of resets controls is 32 times the number of peripheral register banks rather than 32 times the number of clocks. This reduces (drastically) the number of reset controls registered from 10080 (315 clocks * 32) to 224 (6 peripheral register banks * 32). This also fixes a potential crash because trying to use any of the excess reset controls (224-10079) would have caused accesses beyond the array bounds of the peripheral register banks definition array. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Fixes: 6d5b988e7dc5 ("clk: tegra: implement a reset driver") Cc: stable@vger.kernel.org # 3.14+ Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: make tegra_clocks_apply_init_table() arch_initcallPeter De Schrijver2015-02-021-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | tegra_clocks_apply_init_table() needs to be called after the udelay loop has been calibrated (see commit 441f199a37cfd66c5dd8dd45490bd3ea6971117d ("clk: tegra: defer application of init table") for why that is). On existing Tegra SoCs this was done by calling tegra_clocks_apply_init_table() from tegra_dt_init(). To make this also work on ARM64, we need to change this into an initcall. tegra_dt_init() is called from customize_machine which is an arch_initcall. Therefore this should also work on existing 32bit Tegra SoCs. Tested on Tegra20 (ventana), Tegra30 (beaverboard), Tegra124 (jetson TK1) and Tegra132. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> [paul@pwsan.com: tweaked the commit message] Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com>
* clk: tegra: Make clock initialization more robustTomeu Vizoso2014-09-181-2/+7
| | | | | | | | | | | | | Don't abort clock initialization if we cannot match an entry in tegra_clk_init_table to a valid entry in the clk array. Also log a corresponding error message. This was discovered when testing a patch that removed the EMC clock from tegra124_clks but left a mention in tegra_clk_init_table. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Merge tag 'cleanup-for-3.17' of ↵Linus Torvalds2014-08-081-1/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Olof Johansson: "This merge window brings a good size of cleanups on various platforms. Among the bigger ones: - Removal of Samsung s5pc100 and s5p64xx platforms. Both of these have lacked active support for quite a while, and after asking around nobody showed interest in keeping them around. If needed, they could be resurrected in the future but it's more likely that we would prefer reintroduction of them as DT and multiplatform-enabled platforms instead. - OMAP4 controller code register define diet. They defined a lot of registers that were never actually used, etc. - Move of some of the Tegra platform code (PMC, APBIO, fuse, powergate) to drivers/soc so it can be shared with 64-bit code. This also converts them over to traditional driver models where possible. - Removal of legacy gpio-samsung driver, since the last users have been removed (moved to pinctrl) Plus a bunch of smaller changes for various platforms that sort of dissapear in the diffstat for the above. clps711x cleanups, shmobile header file refactoring/moves for multiplatform friendliness, some misc cleanups, etc" * tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (117 commits) drivers: CCI: Correct use of ! and & video: clcd-versatile: Depend on ARM video: fix up versatile CLCD helper move MAINTAINERS: Add sdhci-st file to ARCH/STI architecture ARM: EXYNOS: Fix build breakge with PM_SLEEP=n MAINTAINERS: Remove Kirkwood ARM: tegra: Convert PMC to a driver soc/tegra: fuse: Set up in early initcall ARM: tegra: Always lock the CPU reset vector ARM: tegra: Setup CPU hotplug in a pure initcall soc/tegra: Implement runtime check for Tegra SoCs soc/tegra: fuse: fix dummy functions soc/tegra: fuse: move APB DMA into Tegra20 fuse driver soc/tegra: Add efuse and apbmisc bindings soc/tegra: Add efuse driver for Tegra ARM: tegra: move fuse exports to soc/tegra/fuse.h ARM: tegra: export apb dma readl/writel ARM: tegra: Use a function to get the chip ID ARM: tegra: Sort includes alphabetically ARM: tegra: Move includes to include/soc/tegra ...
| * ARM: tegra: Move includes to include/soc/tegraThierry Reding2014-07-171-1/+2
| | | | | | | | | | | | | | In order to not clutter the include/linux directory with SoC specific headers, move the Tegra-specific headers out into a separate directory. Signed-off-by: Thierry Reding <treding@nvidia.com>
* | clk: tegra: export clock names for debuggingPeter De Schrijver2014-06-301-0/+6
|/ | | | | | | | When writing a module for testing or debugging purposes, there is no way to get hold of clk handles. This patch solves this by exposing all valid clocks as clkdev's for the virtual device tegra-clk-debug. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: implement a reset driverStephen Warren2013-12-111-1/+49
| | | | | | | | | | | | | The Tegra CAR module implements both a clock and reset controller. So far, the driver exposes the clock feature via the common clock API and the reset feature using a custom API. This patch adds an implementation of the common reset framework API (include/linux/reset*.h). The legacy reset implementation will be removed once all drivers have been converted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: Add periph regs bank XPeter De Schrijver2013-11-261-0/+10
| | | | | | | Tegra124 has an extra bank of peripheral clock registers. Add it to the generic peripheral clock code. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: add clkdev registration infraPeter De Schrijver2013-11-261-0/+9
| | | | | | | Add a common infra for registering clkdev. This allows decoupling clk registration from clkdev registration. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: add common infra for DT clocksPeter De Schrijver2013-11-261-0/+9
| | | | | | | Introduce a common infrastructure for sharing clock initialization between SoCs. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver2013-11-261-5/+39
| | | | | | | | | | This patch makes periph_clk_enb_refcnt a global array, dynamically allocated at boottime. It simplifies the macros somewhat and allows clocks common to several Tegra SoCs to be defined in a separate files. Also the clks array becomes global and dynamically allocated which allows the DT registration to be moved to a generic funcion. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: simplify periph clock dataPeter De Schrijver2013-11-261-0/+104
| | | | | | | | | | This patch determines the register bank for clock enable/disable and reset based on the clock ID instead of hardcoding it in the tables describing the clocks. This results in less data to be maintained in the tables, making the code easier to understand. The full benefit of the change will be realized once also other clocktypes will be table based. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: Use common of_clk_init functionPrashant Gaikwad2013-05-311-12/+0
| | | | | | | | | Use common of_clk_init() function for clocks initialization. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: devicetree match for nvidia,tegra114-carPeter De Schrijver2013-04-041-0/+1
| | | | | | Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: provide dummy cpu car opsPeter De Schrijver2013-04-041-1/+2
| | | | | | | | | | | tegra_boot_secondary() relies on some of the car ops. This means having an uninitialized tegra_cpu_car_ops will lead to an early boot panic. Providing a dummy struct avoids this and makes adding Tegra114 clock support in a bisectable way a lot easier. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: defer application of init tableStephen Warren2013-04-041-0/+10
| | | | | | | | | | | | | | | | | The Tegra clock driver is initialized during the ARM machine descriptor's .init_irq() hook. It can't be initialized earlier, since dynamic memory usage is required. It can't be initialized later, since the .init_timer() hook needs the clocks initialized. However, at this time, udelay() doesn't work. The Tegra clock initialization table may enable some PLLs. Enabling a PLL may require usage of udelay(). Hence, this can't happen right when the clock driver is initialized. To solve this, separate the clock driver initialization from the clock table processing, so they can execute at separate times. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: migrate to new clock codePrashant Gaikwad2013-01-281-0/+16
| | | | | | | | | | | | | | | Migrate Tegra clock support to drivers/clk/tegra, this involves moving: 1. definition of tegra_cpu_car_ops to clk.c 2. definition of reset functions to clk-peripheral.c 3. change parent of cpu clock. 4. Remove legacy clock initialization. 5. Initialize clocks using DT. 6. Remove all instance of mach/clk.h Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: use to_clk_periph_gate().] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: add Tegra specific clocksPrashant Gaikwad2013-01-281-0/+69
Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re: storing pointers to stack variables, make a timeout loop more idiomatic, use _clk_pll_disable() not clk_disable_pll() from _program_pll() to avoid redundant lock operations, unified tegra_clk_periph() and tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock registration functions so they don't have the same name as the clock structs, return -EINVAL from clk_plle_enable when matching table rate not found, pass ops to _tegra_clk_register_pll rather than a bool.] Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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