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path: root/drivers/clk/tegra/clk-id.h
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* clk: tegra: Add missing Tegra210 clocksPeter De Schrijver2017-04-041-0/+6
| | | | | | | | iqc1, iqc2, tegra_clk_pll_a_out_adsp, tegra_clk_pll_a_out0_out_adsp, adsp and adsp neon were not modelled. dp2 wasn't modelled for Tegra210. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Define Tegra210 DMIC clocksPeter De Schrijver2017-03-201-1/+4
| | | | | | | | | | Tegra210 has 3 inputs for Digital Microphones (DMICs). Provide the required clocks for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Define Tegra210 DMIC sync clocksPeter De Schrijver2017-03-201-0/+6
| | | | | | | | | | | | Tegra210 has 3 DMIC inputs which can be clocked from the recovered clock of several other audio inputs (eg. i2s0, i2s1, ...). To model this, we add a 3 new clocks similar to the audio* clocks which handle the same function for the I2S and SPDIF clocks. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Add CEC clockPeter De Schrijver2017-03-201-0/+1
| | | | | | | | | This clock is used to clock the HDMI CEC interface. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Fix ISP clock modellingPeter De Schrijver2017-03-201-0/+1
| | | | | | | | | | The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model this as 1 mux/divider clock and child gate clocks. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Squash sor1 safe/brick/src into a single muxThierry Reding2016-06-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sor1 clock on Tegra210 is structured in the following way: +-------+ | pllp |---+ +-------+ | +--------------+ +-----------+ +----| | | sor_safe | +-------+ | | +-----------+ | plld |--------| | | +-------+ | | +-----------+ | sor1_src |-------| | +-------+ | | +-----------+ | plld2 |--------| | | +-------+ | | | +----| | | +-------+ | +--------------+ | | clkm |---+ +-----------+ +-------+ +--------------+ | | | sor1_brick |-------| sor1 | +--------------+ | | +-----------+ This is impractical to represent in a clock tree, though, because there is no name for the mux that has sor_safe and sor1_src as parents. It is also much more cumbersome to deal with the additional mux because users of these clocks (the display driver) would have to juggle with an extra mux for no real reason. To simply things, the above is squashed into two muxes instead, so that it looks like this: +-------+ | pllp |---+ +-------+ | +--------------+ +-----------+ +----| | | sor_safe | +-------+ | | +-----------+ | plld |--------| | | +-------+ | | +-----------+ | sor1_src |-------| sor1 | +-------+ | | +-----------+ | plld2 |--------| | | | +-------+ | | | | +----| | | | +-------+ | +--------------+ | | | clkm |---+ | | +-------+ +--------------+ | | | sor1_brick |-----------+---+ +--------------+ This still very accurately represents the hardware. Note that sor1 has sor1_brick as input twice, that's because bit 1 in the mux selects the sor1_brick irrespective of bit 0. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Add sor_safe clockThierry Reding2016-04-281-0/+1
| | | | | | | | | The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It has a gate bit in the peripheral clock registers. While the SOR is being powered up, sor_safe can be used as the source until the SOR brick can generate its own clock. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Add dpaux1 clockThierry Reding2016-04-281-0/+1
| | | | | | | This clock is of the same type as dpaux and is added to feed into the second DPAUX block used in conjunction with SOR1. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Add the APB2APE audio clock on Tegra210Jon Hunter2016-02-021-0/+1
| | | | | | | | | The APB2APE clock for the audio subsystem is required for powering up the audio power domain and accessing the various modules in this subsystem on Tegra210 devices. Add this clock for Tegra210. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Add support for Tegra210 clocksRhyland Klein2015-12-171-0/+7
| | | | | | | Implement clock support for Tegra210. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: periph: Add new periph clks and muxes for Tegra210Rhyland Klein2015-11-201-1/+67
| | | | | | | | | | | | | | | | | | | | | Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang2015-02-021-2/+0
| | | | | | | | | | | | | PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock. So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
* clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker2014-05-221-0/+1
| | | | | | | | | | | Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker2014-02-171-0/+4
| | | | | | | | The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with 6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114 and Tegra124 to use these clocks instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
* clk: tegra124: Add common clk IDs to clk-id.hPeter De Schrijver2013-11-261-0/+22
| | | | | | | Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: add header for common tegra clock IDsPeter De Schrijver2013-11-261-0/+213
Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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