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path: root/drivers/clk/sunxi
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* clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso2014-12-032-4/+4
* clk: sunxi: gmac-tx-clk mux is not a CLK_MUX_INDEX_BIT muxHans de Goede2014-11-231-1/+6
* clk: sunxi: Implement A31 PLL6 as a divs clock for 2x outputChen-Yu Tsai2014-11-231-12/+16
* clk: sunxi: Specify number of child clocks for divs clocksChen-Yu Tsai2014-11-231-2/+9
* clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driverChen-Yu Tsai2014-11-231-7/+0
* clk: sunxi: unify APB1 clockEmilio López2014-11-111-5/+2
* clk: sunxi: Add support for bus clock gates on Allwinner A80 SoCChen-Yu Tsai2014-10-211-0/+31
* clk: sunxi: Add support for A80 basic bus clocksChen-Yu Tsai2014-10-212-0/+272
* clk: sunxi: make factors clock mux mask configurableChen-Yu Tsai2014-10-215-3/+5
* Merge tag 'sunxi-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kerne...Mike Turquette2014-09-276-156/+485
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| * clk: sunxi: Add sun8i MBUS clock supportChen-Yu Tsai2014-09-272-0/+79
| * clk: sunxi: mod0: Introduce MMC proper phase handlingMaxime Ripard2014-09-271-0/+189
| * clk: sunxi: Move mbus to mod0 fileMaxime Ripard2014-09-272-57/+12
| * clk: sunxi: Move mod0 clock to a file of its ownMaxime Ripard2014-09-273-1/+83
| * clk: sunxi: Introduce mbus compatibleMaxime Ripard2014-09-271-0/+1
| * clk: sunxi: factors: Invert the probing logicMaxime Ripard2014-09-273-99/+113
| * clk: sunxi: add correct divider table for sun4i-apb0 clockChen-Yu Tsai2014-09-131-0/+9
* | clk: Remove .owner field for driverKiran Padwal2014-09-254-4/+0
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* clk: sunxi: staticize structures and arraysEmilio López2014-07-284-5/+5
* clk: sunxi: add __iomem markings to MMIO pointersEmilio López2014-07-282-6/+6
* Merge tag 'sunxi-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kerne...Mike Turquette2014-07-256-43/+227
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| * clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 supportChen-Yu Tsai2014-07-151-0/+5
| * clk: sunxi: sun6i-apb0-gates: use bitmaps for valid gate indicesChen-Yu Tsai2014-07-151-36/+39
| * clk: sunxi: Fix gate indexing for sun6i-a31-apb0-gatesChen-Yu Tsai2014-07-071-1/+5
| * clk: sunxi: Add A23 APB0 divider clock supportChen-Yu Tsai2014-07-072-1/+71
| * clk: sunxi: Add A23 clocks supportChen-Yu Tsai2014-07-041-0/+101
| * clk: sunxi: Add support for table-based divider clocksChen-Yu Tsai2014-07-041-4/+5
| * clk: sunxi: Support factor clocks with N factor starting not from 0Chen-Yu Tsai2014-07-042-1/+2
| * clk: sunxi: move "ahb_sdram" to protected clock listChen-Yu Tsai2014-07-041-5/+3
| * clk: sunxi: register clock gates with clkdevChen-Yu Tsai2014-07-041-0/+1
* | clk: sunxi: fix devm_ioremap_resource error detection codeHimangi Saraogi2014-07-011-1/+1
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* clk: sunxi: add PRCM (Power/Reset/Clock Management) clks supportBoris BREZILLON2014-06-114-0/+411
* clk: sun6i: Protect SDRAM gating bitMaxime Ripard2014-06-111-0/+1
* clk: sun6i: Protect CPU clockMaxime Ripard2014-06-111-0/+1
* clk: sunxi: Rework clock protection codeMaxime Ripard2014-06-111-28/+44
* clk: sunxi: Move the GMAC clock to a file of its ownMaxime Ripard2014-06-113-99/+121
* clk: sunxi: Move the 24M oscillator to a file of its ownMaxime Ripard2014-06-113-57/+74
* clk: sunxi: Remove calls to clk_putMaxime Ripard2014-06-111-6/+2
* clk: sunxi: Implement A31 USB clockMaxime Ripard2014-06-111-0/+6
* Merge tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/...Linus Torvalds2014-06-072-0/+73
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| * clk: sunxi: Fixup clk_sunxi_mmc_phase_control to take a clk rather then a hw_clkHans de Goede2014-05-141-1/+2
| * clk: sunxi: Implement MMC phase controlEmilio López2014-05-051-0/+36
| * clk: sunxi: factors: automatic reparenting supportEmilio López2014-05-051-0/+36
* | clk: sunxi: fix function type for CLK_OF_DECLARERob Herring2014-05-201-1/+1
* | clk: sunxi: avoid double DT matchingRob Herring2014-05-201-2/+1
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* clk: sunxi: fix thinko in commentEmilio López2014-03-191-1/+1
* clk: sunxi: fix some calculationsEmilio López2014-03-191-3/+3
* clk: sunxi: fix A20 PLL4 calculationEmilio López2014-03-191-0/+7
* clk: sunxi: Add new clock compatiblesMaxime Ripard2014-02-181-15/+15
* clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai2014-02-181-0/+96
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