op-kernel-dev - Development kernel branch for OpenPOWER systems

	Commit message (Collapse)	Author	Age	Files	Lines
*	clk: sunxi-ng: gate: Support common pre-dividers	Chen-Yu Tsai	2017-03-06	1	-0/+47
\| \| \| \| \| \| \| \| \| \|	Some clock gates have a pre-divider between the source input and the gate itself. A notable example is the HSIC 12 MHz clock found on the A83T, which has the 24 MHz main oscillator as its input, and a /2 pre-divider. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
*	clk: sunxi-ng: Add gate clock support	Maxime Ripard	2016-07-08	1	-0/+82
	Some clocks in the Allwinner SoCs clocks unit are just simple gates. Add support for those clocks. Since it's a feature that can also be found in more complex clocks, provide a bunch of helpers that can be reused later on. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-5-maxime.ripard@free-electrons.com