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path: root/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
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* clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCMChen-Yu Tsai2017-05-311-1/+3
| | | | | | | | | | | The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock. As such we need to be able to describe this relationship in the device tree. Export the PLL_PERIPH0 clock so we can reference it in the PRCM node. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driverIcenowy Zheng2017-03-061-1/+2
| | | | | | | | | | | | Allwinner H5 is a SoC that features a design which keeps the peripheral compatible with H3, so that it have also a CCU like the one on H3 -- only one bus gate/reset is added, and the mmc sample/output phases are removed because of MMC controller update. Add its support in our existing H3 CCU driver. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi-ng: Add H3 clocksMaxime Ripard2016-07-081-0/+62
Add the list of clocks and resets found in the H3 CCU. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-14-maxime.ripard@free-electrons.com
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