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path: root/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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* Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kern...Stephen Boyd2017-08-231-1/+12
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| * clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3Icenowy Zheng2017-08-041-1/+1
| * clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate changeChen-Yu Tsai2017-08-041-0/+11
* | clk: Convert to using %pOF instead of full_nameRob Herring2017-07-211-2/+1
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* clk: sunxi-ng: Support multiple variable pre-dividersChen-Yu Tsai2017-06-071-5/+5
* clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driverIcenowy Zheng2017-03-061-7/+320
* clk: sunxi-ng: fix PLL_CPUX adjusting on H3Ondrej Jirman2017-01-021-0/+10
* clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocksChen-Yu Tsai2016-11-111-5/+5
* Merge tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/...Stephen Boyd2016-09-141-5/+5
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| * clk: sunxi-ng: mux: support fixed pre-dividers on multiple parentsChen-Yu Tsai2016-08-251-5/+5
* | clk: sunxi-ng: Fix wrong reset register offsetsJorik Jonker2016-08-291-8/+8
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* clk: sunxi-ng: h3: Fix audio clock divider offsetMaxime Ripard2016-07-111-2/+2
* clk: sunxi-ng: Add H3 clocksMaxime Ripard2016-07-081-0/+826
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