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* Merge tag 'v4.6-rockchip-clk2' of ↵Stephen Boyd2016-03-046-61/+83
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull second batch of rockchip clk updates from Heiko Stuebner: Inclusion of the rk3368 fractional dividers into our handling scheme, fixes for missing error-handling in mmc-phase, inverters and cpu-clocks and some more clock-ids. * tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: include downstream muxes into fractional dividers on rk3368 clk: rockchip: set the clock ids for RK3228 HDMI clk: rockchip: set the clock ids for RK3228 VOP clk: rockchip: add the tsadc clocks found on rk3228 SoCs clk: rockchip: add the new clock ids for RK3228 HDMI clk: rockchip: add the new clock ids for RK3228 VOP clk: rockchip: add id of the tsadc clock found on rk3228 SoCs clk: rockchip: fix coding style for clk-cpu.c clk: rockchip: don't return NULL when registering mmc branch fails clk: rockchip: don't return NULL when registering inverter fails clk: rockchip: check grf when waiting pll lock clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
| * clk: rockchip: include downstream muxes into fractional dividers on rk3368Elaine Zhang2016-02-261-37/+60
| | | | | | | | | | | | | | | | During the initial conversion to the newly introduced combined fractional dividers+muxes the rk3368 clocks were left out, so convert them now. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: set the clock ids for RK3228 HDMIYakir Yang2016-02-261-4/+4
| | | | | | | | | | Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: set the clock ids for RK3228 VOPYakir Yang2016-02-261-3/+3
| | | | | | | | | | Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: add the tsadc clocks found on rk3228 SoCsCaesar Wang2016-02-261-2/+2
| | | | | | | | | | | | | | | | This patch adds the needed clocks for rk3228 tsadc. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: fix coding style for clk-cpu.cShawn Lin2016-02-151-1/+1
| | | | | | | | | | | | | | | | | | Fix the issue reported by checkpatch: ERROR: space prohibited before that ',' (ctx:WxW) + writel(clksel->val , cpuclk->reg_base + clksel->reg); Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: don't return NULL when registering mmc branch failsShawn Lin2016-02-151-6/+2
| | | | | | | | | | | | | | | | | | | | Avoid return NULL if rockchip_clk_register_mmc fails, otherwise rockchip_clk_register_branches print "unknown clock type". The acutal case is that it's a known clock type but we fail to regiser it, which may makes user confuse the reason of failure. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: don't return NULL when registering inverter failsShawn Lin2016-02-151-6/+2
| | | | | | | | | | | | | | | | | | | | Avoid return NULL if rockchip_clk_register_inverter fails, otherwise rockchip_clk_register_branches print "unknown clock type". The acutal case is that it's a known clock type but we fail to regiser it, which may makes user confuse the reason of failure. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: check grf when waiting pll lockShawn Lin2016-02-151-0/+5
| | | | | | | | | | | | | | | | | | rockchip_clk_get_grf pass on return value from syscon_regmap_lookup_by_phandle, so we check grf to make sure whether to do the following things or not. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: disable alt_parent clk in err cases when registering cpuclkShawn Lin2016-02-151-2/+4
| | | | | | | | | | | | | | | | Add clk_disable_unprepare to handle cpuclk->alt_parent if rockchip_clk_register_cpuclk fails. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | Merge tag 'v4.6-rockchip-clk1' of ↵Michael Turquette2016-02-157-153/+157
|\ \ | |/ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Introduction of a factor type and a variant containing a gate to be able to also declare factor clocks in their correct place in the clock tree instead of having to register factor clocks in the init callback separately. And as always some more clock-ids and non-regression fixes for mistakes introduced in past kernel releases.
| * clk: rockchip: convert manually created factor clocks to the new typeHeiko Stuebner2016-02-045-98/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up the init code and move the creation of factor clocks to the appropriate positions coming from the clock architecture diagrams. This also unifies the artificial separation of the hclk_vcodec etc clocks again. We do keep the separate definition of some watchdog and usb480m pseudo clocks for now, as they're not real factor clocks from the clock-tree but placeholders for fixes to come (usb480m gets supplied by the missing driver for the new usbphy type and the watchdog-gate is sitting somewhere else together which we cannot model currently). Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: add a factor clock typeHeiko Stuebner2016-02-042-0/+83
| | | | | | | | | | | | | | | | | | | | | | Add a clock type for fixed factor clocks. This allows us to define fixed factor clocks where they appear in the clock hierarchy instead of in the init function. The additional factor_gate type, finally allows us to model some last parts of the clock tree correctly. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: fix parent of hclk_vcodec on rk3036Heiko Stuebner2016-02-041-1/+1
| | | | | | | | | | | | | | hclk_vcodec is a child of aclk_vcodec with the fixed factor clock hclk_vcodec_pre in between and not a child of hclk_disp_pre. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: free memory in error cases when registering clock branchesShawn Lin2016-02-021-2/+7
| | | | | | | | | | | | | | | | Add free memeory if rockchip_clk_register_branch fails. Fixes: a245fecbb806 ("clk: rockchip: add basic infrastructure...") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on ↵Alexander Kochetkov2016-01-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | rk3188 Allow sclk_i2s0 and i2s0_frac to change their parents rate as that the upstream dividers are purely there to feed sclk_i2s0 Tested on radxarock-lite. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: fix wrong mmc phase shift for rk3228Shawn Lin2016-01-281-3/+3
| | | | | | | | | | | | | | | | | | | | mmc sample shift is 0 for rk3228 refer to user manaul. So it's broken if we enable mmc tuning for rk3228. Fixes: 307a2e9ac ("clk: rockchip: add clock controller for rk3228") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: add hclk_cpubus to the list of rk3188 critical clocksAlexander Kochetkov2016-01-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | hclk_cpubus needs to keep running because it is needed for devices like the rom, i2s0 or spdif to be accessible via cpu. Without that all accesses to devices (readl/writel) return wrong data. So add it to the list of critical clocks. Fixes: 78eaf6095cc763c ("clk: rockchip: disable unused clocks") Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Cc: stable@vger.kernel.org # 4.1.x- Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: add tsadc clock on rk3066Paweł Jarosz2016-01-261-1/+1
| | | | | | | | | | | | | | Set clock id for sclk_tsadc gating clock of tsadc in rk3066 Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: fix usbphy-related clocksHeiko Stuebner2016-01-252-19/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The otgphy clocks really only drive the phy blocks. These in turn contain plls that then generate the 480m clocks the clock controller uses to supply some other clocks like uart0, gpu or the video-codec. So fix this structure to actually respect that hirarchy and removed that usb480m fixed-rate clock working as a placeholder till now, as this wouldn't even work if the supplying phy gets turned off while its pll-output gets used elsewhere. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Michael Turquette <mturquette@baylibre.com>
| * clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for i2s_2chzhangqing2016-01-251-1/+1
| | | | | | | | | | | | | | | | I2S_2CH set freq need to select parent and calculate parent freq. so just mark it as the CLK_SET_RATE_PARENT flag. Signed-off-by: zhangqing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8chzhangqing2016-01-251-1/+1
| | | | | | | | | | | | | | | | SPDIF_8CH set freq need to select parent and calculate parent freq. so just mark it as the CLK_SET_RATE_PARENT flag. Signed-off-by: zhangqing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: rk3368: fix edp_24m parentzhangqing2016-01-251-1/+1
| | | | | | | | | | | | | | | | | | | | The edp_24m parent select bit define is: 1'b0:xin24m 1'b1:1'b0(dummy) so adapt the parent sel bit to the currect one. Signed-off-by: zhangqing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: rk3368: fix hdmi_cec gate-registerHeiko Stuebner2016-01-241-1/+1
| | | | | | | | | | | | | | | | | | | | Fix a typo making the sclk_hdmi_cec access a wrong register to handle its gate. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: zhangqing <zhangqing@rock-chips.com> Cc: stable@vger.kernel.org
| * clk: rockchip: rk3368: fix parents of video encoder/decoderHeiko Stuebner2016-01-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | The vdpu and vepu clocks can also be parented to the npll and current parent list also is wrong as it would use the npll as "usbphy" source, so adapt the parent to the correct one. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: zhangqing <zhangqing@rock-chips.com> Cc: stable@vger.kernel.org
| * clk: rockchip: rk3368: fix cpuclk core dividersHeiko Stuebner2016-01-241-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to commit 9880d4277f6a ("clk: rockchip: fix rk3288 cpuclk core dividers") it seems the cpuclk dividers are one to high on the rk3368 as well. And again similar to the previous fix, we opt to make the divider list contain the values to be written to use the same paradigm for them on all supported socs. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: zhangqing <zhangqing@rock-chips.com> Cc: stable@vger.kernel.org
| * clk: rockchip: rk3368: fix cpuclk mux bit of big cpu-clusterHeiko Stuebner2016-01-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Both clusters have their mux bit in bit 7 of their respective register. For whatever reason the big cluster currently lists bit 15 which is definitly wrong. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: zhangqing <zhangqing@rock-chips.com> Cc: stable@vger.kernel.org
| * clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for hclk_vio_busYakir Yang2016-01-241-1/+1
| | | | | | | | | | | | | | | | | | HCLK_VIO_BUS is the noc bus controller clock for display module, due to it shouldn't belong to any driver, but we need it enabled, so just mark it as the CLK_IGNORE_UNUSED flag. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | Merge branch 'clk-fixes' into clk-nextStephen Boyd2016-01-292-26/+26
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * clk-fixes: clk: rockchip: rk3368: fix some clock gates clk: rockchip: rk3036: rename emac ext source clock clk: rockchip: rk3036: fix the div offset for emac clock clk: rockchip: rk3036: fix uarts clock error clk: rockchip: rk3036: fix the FLAGs for clock mux
| * | clk: rockchip: rk3368: fix some clock gatesJianqun xu2016-01-161-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Reference to the Rockchip RK3368 TRM v1.1, some clock gates need to be updated. Signed-off-by: Jianqun xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: rk3036: rename emac ext source clockXing Zheng2016-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is only support rmii in the RK3036, so we should use the correct ext clock name as described in the TRM. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> [update dt-binding document as well] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: rk3036: fix the div offset for emac clockXing Zheng2016-01-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Due to reference to old version TRM, there are incorrect emac clock node. The SEL_21_9 is used for the parent div, the SEL_21_4 is used for the child div. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: rk3036: fix uarts clock errorXing Zheng2016-01-161-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Due to a copy-paste error the uart1 and uart2 clock div set incorrect, fix it. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: rk3036: fix the FLAGs for clock muxXing Zheng2016-01-161-6/+6
| |/ | | | | | | | | | | | | | | The DFLAGS are used for the clock dividers, the CLKSEL_CON flags of COMPOSITE_NODIV type should be MFLAGS. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | clk-divider: make sure read-only dividers do not write to their registerHeiko Stuebner2016-01-291-1/+3
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") removed the special ops struct for read-only clocks and instead opted to handle them inside the regular ops. On the rk3368 this results in breakage as aclkm now gets set a value. While it is the same divider value, the A53 core still doesn't like it, which can result in the cpu ending up in a hang. The reason being that "ACLKENMasserts one clock cycle before the rising edge of ACLKM" and the clock should only be touched when STANDBYWFIL2 is asserted. To fix this, reintroduce the read-only ops but do include the round_rate callback. That way no writes that may be unsafe are done to the divider register in any case. The Rockchip use of the clk_divider_ops is adapted to this split again, as is the nxp, lpc18xx-ccu driver that was included since the original commit. On lpc18xx-ccu the divider seems to always be read-only so only uses the new ops now. Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge branch 'clk-rockchip' into clk-nextMichael Turquette2016-01-024-47/+116
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| * clk: rockchip: fix section mismatches with new child-clocksHeiko Stübner2016-01-024-47/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To model the muxes downstream of fractional dividers we introduced the child property, allowing to describe a direct child clock. The first implementation seems to cause section warnings, as the core clock-tree is marked as initdata while the data pointed to from the child element is not. While there may be some way to also set that missing property in the inline notation I didn't find it, so to actually fix the issue for now move the sub-definitions into separate declarations that can have their own __initdata properties. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | Merge branch 'clk-rockchip' into clk-nextMichael Turquette2015-12-235-105/+235
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| * clk: rockchip: rk3036: include downstream muxes into fractional dividersXing Zheng2015-12-231-17/+17
| | | | | | | | | | | | | | | | | | | | | | Use the newly introduced possibility to combine the fractional dividers with their downstream muxes for all fractional dividers on currently supported RK3036 SoCs. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * clk: rockchip: Allow the RK3288 SPDIF clocks to change their parentSjoerd Simons2015-12-231-8/+8
| | | | | | | | | | | | | | | | | | | | The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288 SoCs only feed those clocks, allow those clocks to change their parents all the way up the hierarchy. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * clk: rockchip: include downstream muxes into fractional dividersHeiko Stuebner2015-12-232-72/+74
| | | | | | | | | | | | | | | | | | | | | | Use the newly introduced possibility to combine the fractional dividers with their downstream muxes for all fractional dividers on currently supported Rockchip SoCs. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * clk: rockchip: handle mux dependency of fractional dividersHeiko Stuebner2015-12-232-14/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | clk: rockchip: only enter pll slow-mode directly before reboots on rk3288Heiko Stuebner2015-12-217-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") states, switching the PLLs to slow-mode is only necessary when rebooting using the soft-reset done through the CRU. The dwc2 controllers used create really big number of interrupts in special constellations involving usb-hubs and their number is so high, it can even overwhelm the interrupt handler if the cpu-speed os to low. Right now the PLLs are put into slow-mode in a shutdown syscore_ops callback which means it happens on all reboots (not only the soft-reset ones) and even on poweroff actions. This can result in the system not powering off and getting stuck instead, so we should move the slow-mode change nearer to the actual reboot action. For this we introduce the possiblity to also set a callback that gets called from the restart-handler directly prior to restarting the system and move the shutdown-callback to this new option. With this the slow-mode switch is done only on the necessary reboots and also has a smaller possibility of causing artifacts. Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com> Reviewed-by: Douglas Anderson <dianders@chromium.org>
* | clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for aclk_vioYakir Yang2015-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | ACLK_VIO is the noc bus clock for display module, display cann't read data from ddr without this clock enabled. Due to it shouldn't belong to any driver, but we need it enabled, so just mark it as the CLK_IGNORE_UNUSED flag. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | clk: rockchip: use rk3288-efuse clock idsZhengShunQian2015-12-121-2/+2
| | | | | | | | | | | | | | | | Reference the newly added efuse clock-ids in the clock-tree. Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | clk: rockchip: add clock controller for rk3228Jeffy Chen2015-12-123-1/+689
| | | | | | | | | | | | | | Add the clock tree definition for the new rk3228 SoC. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | clk: rockchip: allow more than 2 parents for cpuclkJeffy Chen2015-12-091-2/+2
|/ | | | | | | | RK3228's armclk has 3 parents, so allow cpuclk to have more than 2 parents. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* clk: rockchip: fix rk3368 cpuclk divider offsetsHeiko Stuebner2015-12-031-2/+2
| | | | | | | | | Due to a copy-paste error the the rk3368 cpuclk settings were acessing rk3288-specific register offsets. This never caused problems till now, as cpu frequency scaling in't used currently at all. Reported-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* clk: rockchip: protect rk3368 aclk_bus and aclk_peri clocksJianqun xu2015-12-021-0/+2
| | | | | | | | | Add aclk_bus and aclk_peri to the list of rk3368 critical clocks, which are the base clocks that supply for all peripherals, never to be disabled automatically. Signed-off-by: Jianqun xu <jay.xu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* clk: rockchip: Force rk3368 PWM clock (and its parents) onCaesar Wang2015-12-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most rk3368 boards (especially those with Pmic that followed the lead from rk3368-evb-act8846) have a PWM regulator on them for vdd_logic. This is the main voltage for all kinds of misc stuff including the memory controller. On these boards it is critically important to make sure that the PWM never ever glitches and never loses its clock. Any glitch could crash the system. Right now there are no users of the PWM regulator and also Linux thinks that the PWM regulator is disabled. Things happen to work because firmware configured the PWM and Linux doesn't touch it. ..and the PWM's clock is marked as "ignore unused". ...but things _stop_ working if we turn off serial console. Why? Because: 1. Serial console shares a parent clock with the PWM (pclk_cpu) 2. If we have no serial console then nobody is holding pclk_cpu on at reboot time. It gets disabled. We need to fix a lot of the above problems, but until we get everything right the cleanest "hack" seems like it is to just keep the "rk_pwm" clock on always. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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