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path: root/drivers/clk/rockchip/clk-rk3368.c
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* clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCsRomain Perier2017-10-141-1/+1
| | | | | | | | This exports the clock for the pclk gate of the eFuse that is part of the RK3368 SoCs. So we can use it from the dt-bindings. Signed-off-by: Romain Perier <romain.perier@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* clk: rockchip: mark some special clk as critical on rk3368Elaine Zhang2017-06-021-1/+4
| | | | | | | | | | | | | The jtag clk no driver to handle them. But this clk need enable,so make it as critical. The ddrphy/ddrupctl clks no driver to handle them, Chip design requirements for these clock to always on, The pmu_hclk_otg0 is Chip design defect, must be always on, Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* clk: rockchip: mark some rk3368 core-clks as criticalElaine Zhang2017-03-101-0/+3
| | | | | | | Mark pclk_pd_alive, pclk_peri, hclk_peri as critical Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* clk: rockchip: export SCLK_TIMERXX id for timers on rk3368Elaine Zhang2017-03-101-12/+12
| | | | | Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* clk: rockchip: release io resource when failing to init clkShawn Lin2016-03-271-0/+1
| | | | | | | | We should call iounmap to relase reg_base since it's not going to be used any more if failing to init clk. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* clk: rockchip: Add support for multiple clock providersXing Zheng2016-03-271-7/+14
| | | | | | | | | | | There are need to support Multi-CRUs probability in future, but it is not supported on the current Rockchip Clock Framework. Therefore, this patch add support a provider as the parameter handler when we call the clock register functions for per CRU. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* clk: rockchip: allow varying mux parameters for cpuclk pll-sourcesXing Zheng2016-03-271-0/+6
| | | | | | | | | | | | Thers are only two parent PLLs that APLL and GPLL for core on the previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed GPLL as alternate parent when core is switching freq. Since RK3399 big.LITTLE architecture, we need to select and adapt more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* Merge tag 'v4.6-rockchip-clk2' of ↵Stephen Boyd2016-03-041-37/+60
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull second batch of rockchip clk updates from Heiko Stuebner: Inclusion of the rk3368 fractional dividers into our handling scheme, fixes for missing error-handling in mmc-phase, inverters and cpu-clocks and some more clock-ids. * tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: include downstream muxes into fractional dividers on rk3368 clk: rockchip: set the clock ids for RK3228 HDMI clk: rockchip: set the clock ids for RK3228 VOP clk: rockchip: add the tsadc clocks found on rk3228 SoCs clk: rockchip: add the new clock ids for RK3228 HDMI clk: rockchip: add the new clock ids for RK3228 VOP clk: rockchip: add id of the tsadc clock found on rk3228 SoCs clk: rockchip: fix coding style for clk-cpu.c clk: rockchip: don't return NULL when registering mmc branch fails clk: rockchip: don't return NULL when registering inverter fails clk: rockchip: check grf when waiting pll lock clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
| * clk: rockchip: include downstream muxes into fractional dividers on rk3368Elaine Zhang2016-02-261-37/+60
| | | | | | | | | | | | | | | | During the initial conversion to the newly introduced combined fractional dividers+muxes the rk3368 clocks were left out, so convert them now. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | Merge tag 'v4.6-rockchip-clk1' of ↵Michael Turquette2016-02-151-49/+33
|\ \ | |/ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Introduction of a factor type and a variant containing a gate to be able to also declare factor clocks in their correct place in the clock tree instead of having to register factor clocks in the init callback separately. And as always some more clock-ids and non-regression fixes for mistakes introduced in past kernel releases.
| * clk: rockchip: convert manually created factor clocks to the new typeHeiko Stuebner2016-02-041-22/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up the init code and move the creation of factor clocks to the appropriate positions coming from the clock architecture diagrams. This also unifies the artificial separation of the hclk_vcodec etc clocks again. We do keep the separate definition of some watchdog and usb480m pseudo clocks for now, as they're not real factor clocks from the clock-tree but placeholders for fixes to come (usb480m gets supplied by the missing driver for the new usbphy type and the watchdog-gate is sitting somewhere else together which we cannot model currently). Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for i2s_2chzhangqing2016-01-251-1/+1
| | | | | | | | | | | | | | | | I2S_2CH set freq need to select parent and calculate parent freq. so just mark it as the CLK_SET_RATE_PARENT flag. Signed-off-by: zhangqing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8chzhangqing2016-01-251-1/+1
| | | | | | | | | | | | | | | | SPDIF_8CH set freq need to select parent and calculate parent freq. so just mark it as the CLK_SET_RATE_PARENT flag. Signed-off-by: zhangqing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: rk3368: fix edp_24m parentzhangqing2016-01-251-1/+1
| | | | | | | | | | | | | | | | | | | | The edp_24m parent select bit define is: 1'b0:xin24m 1'b1:1'b0(dummy) so adapt the parent sel bit to the currect one. Signed-off-by: zhangqing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: rk3368: fix hdmi_cec gate-registerHeiko Stuebner2016-01-241-1/+1
| | | | | | | | | | | | | | | | | | | | Fix a typo making the sclk_hdmi_cec access a wrong register to handle its gate. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: zhangqing <zhangqing@rock-chips.com> Cc: stable@vger.kernel.org
| * clk: rockchip: rk3368: fix parents of video encoder/decoderHeiko Stuebner2016-01-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | The vdpu and vepu clocks can also be parented to the npll and current parent list also is wrong as it would use the npll as "usbphy" source, so adapt the parent to the correct one. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: zhangqing <zhangqing@rock-chips.com> Cc: stable@vger.kernel.org
| * clk: rockchip: rk3368: fix cpuclk core dividersHeiko Stuebner2016-01-241-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to commit 9880d4277f6a ("clk: rockchip: fix rk3288 cpuclk core dividers") it seems the cpuclk dividers are one to high on the rk3368 as well. And again similar to the previous fix, we opt to make the divider list contain the values to be written to use the same paradigm for them on all supported socs. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: zhangqing <zhangqing@rock-chips.com> Cc: stable@vger.kernel.org
| * clk: rockchip: rk3368: fix cpuclk mux bit of big cpu-clusterHeiko Stuebner2016-01-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Both clusters have their mux bit in bit 7 of their respective register. For whatever reason the big cluster currently lists bit 15 which is definitly wrong. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: zhangqing <zhangqing@rock-chips.com> Cc: stable@vger.kernel.org
* | clk: rockchip: rk3368: fix some clock gatesJianqun xu2016-01-161-13/+13
|/ | | | | | | | | Reference to the Rockchip RK3368 TRM v1.1, some clock gates need to be updated. Signed-off-by: Jianqun xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* clk: rockchip: only enter pll slow-mode directly before reboots on rk3288Heiko Stuebner2015-12-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") states, switching the PLLs to slow-mode is only necessary when rebooting using the soft-reset done through the CRU. The dwc2 controllers used create really big number of interrupts in special constellations involving usb-hubs and their number is so high, it can even overwhelm the interrupt handler if the cpu-speed os to low. Right now the PLLs are put into slow-mode in a shutdown syscore_ops callback which means it happens on all reboots (not only the soft-reset ones) and even on poweroff actions. This can result in the system not powering off and getting stuck instead, so we should move the slow-mode change nearer to the actual reboot action. For this we introduce the possiblity to also set a callback that gets called from the restart-handler directly prior to restarting the system and move the shutdown-callback to this new option. With this the slow-mode switch is done only on the necessary reboots and also has a smaller possibility of causing artifacts. Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com> Reviewed-by: Douglas Anderson <dianders@chromium.org>
* clk: rockchip: fix rk3368 cpuclk divider offsetsHeiko Stuebner2015-12-031-2/+2
| | | | | | | | | Due to a copy-paste error the the rk3368 cpuclk settings were acessing rk3288-specific register offsets. This never caused problems till now, as cpu frequency scaling in't used currently at all. Reported-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* clk: rockchip: protect rk3368 aclk_bus and aclk_peri clocksJianqun xu2015-12-021-0/+2
| | | | | | | | | Add aclk_bus and aclk_peri to the list of rk3368 critical clocks, which are the base clocks that supply for all peripherals, never to be disabled automatically. Signed-off-by: Jianqun xu <jay.xu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* clk: rockchip: Force rk3368 PWM clock (and its parents) onCaesar Wang2015-12-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most rk3368 boards (especially those with Pmic that followed the lead from rk3368-evb-act8846) have a PWM regulator on them for vdd_logic. This is the main voltage for all kinds of misc stuff including the memory controller. On these boards it is critically important to make sure that the PWM never ever glitches and never loses its clock. Any glitch could crash the system. Right now there are no users of the PWM regulator and also Linux thinks that the PWM regulator is disabled. Things happen to work because firmware configured the PWM and Linux doesn't touch it. ..and the PWM's clock is marked as "ignore unused". ...but things _stop_ working if we turn off serial console. Why? Because: 1. Serial console shares a parent clock with the PWM (pclk_cpu) 2. If we have no serial console then nobody is holding pclk_cpu on at reboot time. It gets disabled. We need to fix a lot of the above problems, but until we get everything right the cleanest "hack" seems like it is to just keep the "rk_pwm" clock on always. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* clk: rockchip: add critical clock for rk3368Heiko Stübner2015-09-141-0/+6
| | | | | | | | | | Again a result of the gpio-clock-liberation the rk3368 needs the pclk_pd_pmu marked as critical, to boot successfully. Reported-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: rockchip: add rk3368 clock controllerHeiko Stuebner2015-07-061-0/+881
Describe the clock tree and software resets of the rk3368 ARM64 SoC Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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