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* clk/Renesas-MSTP: Use kmalloc_array() in cpg_mstp_clocks_init()Markus Elfring2016-09-161-1/+1
| | | | | | | | | | | | A multiplication for the size determination of a memory allocation indicated that an array data structure should be processed. Thus use the corresponding function "kmalloc_array". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'clk-renesas-for-v4.9-tag3' of ↵Stephen Boyd2016-09-143-2/+32
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull renesas clk driver updates from Geert Uytterhoeven: - External crystal selection for RZ/A1, - CMT clocks for R-Car H3 and M3-W, - RAVB and Thermal clocks for R-Car M3-W. * tag 'clk-renesas-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add CMT clocks clk: renesas: r8a7795: Add CMT clocks clk: renesas: r8a7796: Add RAVB clock clk: renesas: r8a7796: Add THS/TSC clock clk: renesas: rz: Select EXTAL vs USB clock
| * clk: renesas: r8a7796: Add CMT clocksBui Duc Phuc2016-09-121-0/+4
| | | | | | | | | | | | | | This patch adds CMT module clocks for r8a7796 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a7795: Add CMT clocksBui Duc Phuc2016-09-121-0/+4
| | | | | | | | | | | | | | This patch adds CMT module clocks for r8a7795 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a7796: Add RAVB clockLaurent Pinchart2016-09-121-0/+1
| | | | | | | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a7796: Add THS/TSC clockKhiem Nguyen2016-09-051-0/+1
| | | | | | | | | | Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: rz: Select EXTAL vs USB clockChris Brandt2016-09-051-2/+22
| | | | | | | | | | | | | | | | Check the MD_CLK pin to determine the current clock mode in order to set the pll clock parent correctly. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | Merge tag 'clk-renesas-for-v4.9-tag2' of ↵Stephen Boyd2016-08-301-0/+18
|\ \ | |/ | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull renesas r8a7796 SDHI clock support from Geert Uytterhoeven: Add all clocks needed to use the SDHI interfaces on the Renesas R-Car M3-W (r8a7796) SoC. * tag 'clk-renesas-for-v4.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add SDIF clocks clk: renesas: r8a7796: Add GPIO clocks
| * clk: renesas: r8a7796: Add SDIF clocksSimon Horman2016-08-231-0/+10
| | | | | | | | | | | | | | | | | | This patch adds SDIF clocks for R8A7796 SoC. Based on work by Ai Kyuse and Yoshihiro Shimoda for the r8a7795 SoC. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a7796: Add GPIO clocksTakeshi Kihara2016-08-191-0/+8
| | | | | | | | | | | | | | | | Add GPIO clocks for the R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | Merge tag 'clk-renesas-for-v4.9-tag1' of ↵Stephen Boyd2016-08-181-0/+7
|\ \ | |/ | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Merge r8a7796 watchdog clk support from Geert Uytterhoeven: Add all clocks related to the Watchdog Timer (WDT) controller on the Renesas R-Car M3-W (r8a7796) SoC. * tag 'clk-renesas-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add watchdog module clock clk: renesas: r8a7796: Add watchdog core clocks
| * clk: renesas: r8a7796: Add watchdog module clockGeert Uytterhoeven2016-08-091-0/+1
| | | | | | | | | | | | | | Add the module clock for the Watchdog Timer (WDT) controller on the Renesas R-Car M3-W (r8a7796) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a7796: Add watchdog core clocksGeert Uytterhoeven2016-08-091-0/+6
| | | | | | | | | | | | | | Add all core clocks related to the Watchdog Timer (WDT) controller on the Renesas R-Car M3-W (r8a7796) SoC: OSC, Internal RCLK, and RCLK. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r8a7795: Fix SD clocksYoshihiro Shimoda2016-08-111-4/+5
|/ | | | | | | | | | | | | | | | According to the datasheet, SDn clocks are from the SDSRC clock. And the SDSRC has a 1/2 divider. So, we should have ".sdsrc" as an internal core clock. Otherwise, since the sdhi driver will calculate clock for a sd card using the wrong parent clock rate, and then performance will be not good. Fixes: 90c073e53909da85 ("clk: shmobile: r8a7795: Add SD divider support") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: stable@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: r8a7795: Add THS/TSC clockKhiem Nguyen2016-06-211-0/+1
| | | | | Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add DRIF clockRamesh Shanmugasundaram2016-06-211-0/+8
| | | | | | | This patch adds DRIF module clocks for r8a7795 SoC. Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Correct lvds clock parentGeert Uytterhoeven2016-06-211-1/+1
| | | | | | | | | | | According to the latest information, the parent clock of the LVDS module clock is the S0D4 clock, not the S2D1 clock. Note that this change has no influence on actual operation, as the rcar-du LVDS encoder driver doesn't use the parent clock's rate. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* clk: renesas: r8a7795: Provide FDP1 clocksKieran Bingham2016-06-211-0/+3
| | | | | | Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kieran Bingham <kieran@bingham.xyz> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Add R8A7792 supportSergei Shtylyov2016-06-212-0/+2
| | | | | | | Renesas R-Car V2H (R8A7792) clocks are handled by R-Car gen2 clock driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add support for R-Car M3-WGeert Uytterhoeven2016-06-065-0/+201
| | | | | | | | Initial support for R-Car M3-W (r8a7796), including basic core clocks, and SCIF2 (console) and INTC-AP (GIC) module clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: cpg-mssr: Extract common R-Car Gen3 support codeGeert Uytterhoeven2016-06-064-356/+408
| | | | | | | | | | | | | Extract the code to support parts common to all members of the R-Car Gen3 SoC family into a separate file, to ease sharing among SoC-specific drivers. Note that while the cpg_pll_configs[] arrays and the selection of the config based on the MODE bits are identical on R-Car H3 and R-Car M3-W, they are not common, and may be different on other R-Car Gen3 SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: cpg-mssr: Use always-on governor for Clock DomainGeert Uytterhoeven2016-04-281-1/+1
| | | | | | | | | | | | | | | | As a pure Clock Domain does not have the concept of powering the domain itself, the CPG/MSTP driver does not provide power_off() and power_on() callbacks. However, the genpd core may still perform a dummy power down, causing /sys/kernel/debug/pm_genpd/pm_genpd_summary to report the domain's status being "off-0". Use the always-on governor to make sure the domain is never powered down, and always shows up as "on" in pm_genpd_summary. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
* clk: renesas: cpg-mssr: Postpone call to pm_genpd_init()Geert Uytterhoeven2016-04-281-1/+1
| | | | | | | | | All local setup of the generic_pm_domain structure should have been completed before calling pm_genpd_init(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
* clk: renesas: mstp: Use always-on governor for Clock DomainGeert Uytterhoeven2016-04-281-1/+1
| | | | | | | | | | | | | | | | As a pure Clock Domain does not have the concept of powering the domain itself, the CPG/MSTP driver does not provide power_off() and power_on() callbacks. However, the genpd core may still perform a dummy power down, causing /sys/kernel/debug/pm_genpd/pm_genpd_summary to report the domain's status being "off-0". Use the always-on governor to make sure the domain is never powered down, and always shows up as "on" in pm_genpd_summary. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
* clk: renesas: mstp: Postpone call to pm_genpd_init()Geert Uytterhoeven2016-04-281-2/+1
| | | | | | | | | All local setup of the generic_pm_domain structure should have been completed before calling pm_genpd_init(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
* clk: renesas: r8a7795: Add VIN clocksNiklas Söderlund2016-04-261-0/+8
| | | | | Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add CSI2 clocksNiklas Söderlund2016-04-261-0/+5
| | | | | Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev()Geert Uytterhoeven2016-04-201-6/+12
| | | | | | | | | | | | | | | | | | | | The R-Car SYSC PM Domain driver has to power manage devices in power areas using clocks. To reuse code and to share knowledge of clocks suitable for power management, this is ideally done through the existing cpg_mssr_attach_dev() and cpg_mssr_detach_dev() callbacks. Hence these callbacks can no longer rely on their "domain" parameter pointing to the CPG/MSSR Clock Domain. To handle this, keep a pointer to the clock domain in a static variable. cpg_mssr_attach_dev() has to support probe deferral, as the R-Car SYSC PM Domain may be initialized, and devices may be added to it, before the CPG/MSSR Clock Domain is initialized. Dummy callbacks are provided for the case where CPG/MSTP support is not included, so the rcar-sysc driver won't have to care about this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP supportGeert Uytterhoeven2016-04-202-12/+30
| | | | | | | | | | | | | | Currently the decision whether to build the renesas-cpg-mssr and clk-mstp drivers is handled by Makefile logic. However, the rcar-sysc driver will need to know whether CPG/MSSR and/or CPG/MSTP support are available or not. To avoid having to duplicate this logic, move it to Kconfig. Provide non-visible CLK_RENESAS_CPG_MSSR and CLK_RENESAS_CPG_MSTP Kconfig symbols, which can be used by both Makefiles and C code. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* clk: renesas: mstp: Clarify cpg_mstp_{at,de}tach_dev() domain parameterGeert Uytterhoeven2016-04-071-2/+2
| | | | | | | | | | | Make it clear that the "domain" parameter of the cpg_mstp_attach_dev() and cpg_mstp_detach_dev() functions is not used. The cpg_mstp_attach_dev() and cpg_mstp_detach_dev() callbacks are not only used by the CPG/MSTP Clock Domain driver, but also by the R-Mobile SYSC PM Domain driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Drop check for CONFIG_PM_GENERIC_DOMAINS_OFGeert Uytterhoeven2016-04-071-11/+0
| | | | | | | | | | As of commit 71d076ceb245f0d9 ("ARM: shmobile: Enable PM and PM_GENERIC_DOMAINS for SoCs with PM Domains"), CONFIG_PM_GENERIC_DOMAINS_OF is always enabled for SoCs with a CPG/MSSR block. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* clk: renesas: mstp: Drop check for CONFIG_PM_GENERIC_DOMAINS_OFGeert Uytterhoeven2016-04-071-3/+0
| | | | | | | | | | As of commit 71d076ceb245f0d9 ("ARM: shmobile: Enable PM and PM_GENERIC_DOMAINS for SoCs with PM Domains"), CONFIG_PM_GENERIC_DOMAINS_OF is always enabled for SoCs with MSTP clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* clk: renesas: r8a7795: add RWDT clockWolfram Sang2016-04-061-0/+1
| | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: add R clkWolfram Sang2016-04-061-0/+16
| | | | | | | | | | | | R can select between two parents. We deal with it like this: During initialization, check if EXTALR is populated. If so, use it for R. If not, use R_Internal. clk_mux doesn't help here because we don't want to switch parents depending on the clock rate. The clock rate (and source) should stay constant for the watchdog, so I think a setup like this during initialization makes sense. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: add OSC and RINT clocksWolfram Sang2016-04-061-0/+5
| | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: add generic support for read-only DIV6 clocksWolfram Sang2016-04-062-6/+15
| | | | | | | | | Gen3 has two clocks (OSC and R) which look like a DIV6 clock but their divider value is read-only and depends on MD pins at bootup. Add support for such clocks by reading the value and adding a fixed clock. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: make SD clk definition specific for GEN3Wolfram Sang2016-03-292-7/+7
| | | | | | | | | About SD clocks: The clock type is Gen3 specific, the callbacks are all Gen3 specific; I think the clock definition should also be Gen3 specific and not in the general header file. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: add PWM clockUlrich Hecht2016-03-291-0/+1
| | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: div6: use RENESAS for #defineSimon Horman2016-03-151-2/+2
| | | | | | | | | | | | | | | Name the #define guarding compilation of this header __RENESAS_CLK_DIV6_H__ rather than __SHMOBILE_CLK_DIV6_H__. This is a follow-up to renaming the directory in which this file lives from shmobile to renesas which is in turn part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: Rename header file renesas.hSimon Horman2016-03-158-8/+8
| | | | | | | | | | | | | This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Along with the above mentioned Kconfig changes it seems appropriate to also rename files. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: move drivers to renesas directorySimon Horman2016-03-0315-0/+3670
This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Along with the above mentioned Kconfig changes it seems appropriate to also rename directories that only hold drivers for such SoCs. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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