| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | CLK: Pistachio: Register external clock gates | Andrew Bresticker | 2015-03-31 | 1 | -0/+21 |
| * | CLK: Pistachio: Register system interface gate clocks | Andrew Bresticker | 2015-03-31 | 1 | -0/+42 |
| * | CLK: Pistachio: Register peripheral clocks | Andrew Bresticker | 2015-03-31 | 1 | -0/+67 |
| * | CLK: Pistachio: Register core clocks | Andrew Bresticker | 2015-03-31 | 2 | -0/+200 |
| * | CLK: Pistachio: Add PLL driver | Andrew Bresticker | 2015-03-31 | 3 | -0/+452 |
| * | CLK: Add basic infrastructure for Pistachio clocks | Andrew Bresticker | 2015-03-31 | 3 | -0/+265 |
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index : op-kernel-dev | |
| Development kernel branch for OpenPOWER systems | Raptor Engineering, LLC |
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