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path: root/drivers/clk/meson
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* clk: meson: gxbb: Add VPU and VAPB clocks dataNeil Armstrong2017-10-201-0/+292
* clk: meson: gxbb: Add VPU and VAPB clockidsNeil Armstrong2017-10-201-1/+5
* Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into cl...Stephen Boyd2017-08-2310-251/+685
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| * clk: meson: gxbb-aoclk: Add CEC 32k clockNeil Armstrong2017-08-044-2/+231
| * clk: meson: gxbb-aoclk: Switch to regmap for register accessNeil Armstrong2017-08-044-23/+95
| * clk: meson: gxbb: Add sd_emmc clk0 clocksJerome Brunet2017-08-041-0/+177
| * clk: meson: gxbb: fix clk_mclk_i958 divider flagsJerome Brunet2017-08-041-3/+4
| * clk: meson: gxbb: fix meson cts_amclk divider flagsJerome Brunet2017-08-041-1/+2
| * clk: meson: meson8b: register the built-in reset controllerMartin Blumenstingl2017-08-043-13/+156
| * clk: meson: gxbb: Add sd_emmc clk0 clkidsJerome Brunet2017-08-041-2/+8
| * clk: meson-gxbb: expose almost every clock in the bindingsJerome Brunet2017-08-041-110/+7
| * clk: meson8b: expose every clock in the bindingsJerome Brunet2017-08-041-99/+4
| * clk: meson: gxbb: fix protection against undefined clksJerome Brunet2017-08-041-0/+2
| * clk: meson: meson8b: fix protection against undefined clksJerome Brunet2017-08-041-0/+1
* | clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet2017-08-014-0/+18
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* Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into ...Stephen Boyd2017-06-164-19/+25
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| * clk: meson: gxbb: add all clk81 parentsJerome Brunet2017-06-161-5/+8
| * Merge branch 'next/headers' into next/driversJerome Brunet2017-06-161-10/+10
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| | * clk: meson8b: export the ethernet gate clockMartin Blumenstingl2017-06-121-1/+1
| | * clk: meson8b: export the USB clocksMartin Blumenstingl2017-06-121-5/+5
| | * clk: meson8b: export the gate clock for the HW random number generatorMartin Blumenstingl2017-06-121-1/+1
| | * clk: meson8b: export the SDIO clockMartin Blumenstingl2017-06-121-1/+1
| | * clk: meson8b: export the SAR ADC clocksMartin Blumenstingl2017-06-121-2/+2
| * | clk: meson: meson8b: add compatibles for Meson8 and Meson8m2Martin Blumenstingl2017-06-122-4/+7
* | | clk: meson-gxbb: Add const to some parent name arraysStephen Boyd2017-06-021-3/+3
* | | Merge tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson into cl...Stephen Boyd2017-06-023-74/+73
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| * | clk: meson-gxbb: Add EE 32K Clock for CECNeil Armstrong2017-05-292-1/+58
| * | clk: gxbb: remove CLK_IGNORE_UNUSED from clk81Jerome Brunet2017-05-291-1/+1
| * | clk: meson: meson8b: mark clk81 as criticalMartin Blumenstingl2017-05-291-1/+1
| * | clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driverMartin Blumenstingl2017-05-292-62/+4
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| * clk: meson-gxbb: un-export the CPU clockMartin Blumenstingl2017-05-291-1/+1
| * clk: meson-gxbb: expose UART clocksHelmut Klein2017-05-291-3/+3
| * clk: meson-gxbb: expose SPICC gateNeil Armstrong2017-05-291-1/+1
| * clk: meson-gxbb: expose spdif master clockJerome Brunet2017-05-291-2/+2
| * clk: meson-gxbb: expose i2s master clockJerome Brunet2017-05-291-1/+1
| * clk: meson-gxbb: expose spdif clock gatesJerome Brunet2017-05-291-2/+2
* | clk: meson: gxbb: fix build error without RESET_CONTROLLERTobias Regnery2017-05-161-0/+1
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2017-05-109-49/+1150
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| * clk: meson: mpll: use 64bit math in rate_from_paramsMartin Blumenstingl2017-04-071-1/+1
| * clk: meson: mpll: fix division by zero in rate_from_paramsMartin Blumenstingl2017-04-071-11/+15
| * clk: meson: gxbb: add cts_i958 clockJerome Brunet2017-04-072-1/+23
| * clk: meson: gxbb: add cts_mclk_i958Jerome Brunet2017-04-072-1/+56
| * clk: meson: gxbb: add cts_amclkJerome Brunet2017-04-072-1/+71
| * clk: meson: add audio clock divider supportJerome Brunet2017-04-073-1/+155
| * clk: meson: gxbb: protect against holes in the onecell_data arrayJerome Brunet2017-04-071-0/+4
| * Merge branch 'v4.12/clk-drivers' into v4.12/clkKevin Hilman2017-04-047-48/+840
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| | * clk: meson-gxbb: Add GXL/GXM GP0 VariantNeil Armstrong2017-04-042-28/+275
| | * clk: meson-gxbb: Add GP0 PLL init parametersNeil Armstrong2017-04-041-0/+13
| | * clk: meson: Add support for parameters for specific PLLsNeil Armstrong2017-04-042-2/+74
| | * clk: meson-gxbb: Add MALI clocksNeil Armstrong2017-04-041-0/+139
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