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path: root/drivers/clk/meson/Makefile
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* clk: gxbb: add AmLogic GXBB clk controller driverMichael Turquette2016-06-221-0/+1
| | | | | | | | | | The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* clk: meson: add mpll supportMichael Turquette2016-06-221-1/+1
| | | | | | | | | | | MPLLs are adjustable rate clocks derived from PLLs. On both Meson8b and GXBB they appear to be only derived from fixed_pll. Add support for these clock types so that they can be added to their respective drivers. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* clk: meson: only build selected platformsMichael Turquette2016-06-221-2/+2
| | | | | | | | | | Break the AmLogic clock code up so that only the necessary parts are compiled and linked. The core code is selected by both arm and arm64 builds with COMMON_CLK_AMLOGIC. The individual drivers have their own config options as well. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* clk: meson8b: clean up composite clocksMichael Turquette2016-06-221-1/+1
| | | | | | | | | | | | | Remove the composite clock registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. To preserve git bisect this patch also flips the switch and starts using of_clk_add_hw_provider instead of the deprecated meson_clk_register_clks method. As a byproduct clk.c can be deleted. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* clk: meson8b: Add support for Meson8b clocksCarlo Caione2015-06-051-0/+1
| | | | | | | | This patch adds support for the basic clocks found on the Amlogic Meson8b SoCs. Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: meson: Add support for Meson clock controllerCarlo Caione2015-06-051-0/+5
This patchset adds the infrastructure for registering and managing the core clocks found on Amlogic MesonX SoCs. In particular: - PLLs - CPU clock - Fixed rate clocks, fixed factor clocks, ... Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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