| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: keystone: add support for post divider register for main pll | Murali Karicheri | 2015-06-18 | 1 | -2/+18 |
| * | clk: keystone: gate: fix clk_init_data initialization | Ivan Khoronzhuk | 2014-02-10 | 1 | -0/+1 |
| * | clk: keystone: gate: fix error handling on init | Grygorii Strashko | 2013-12-10 | 1 | -4/+8 |
| * | clk: keystone: use clkod register bits for postdiv | Murali Karicheri | 2013-12-10 | 1 | -4/+20 |
| * | clk: keystone: Build Keystone clock drivers | Santosh Shilimkar | 2013-10-07 | 1 | -0/+1 |
| * | clk: keystone: Add gate control clock driver | Santosh Shilimkar | 2013-10-07 | 1 | -0/+264 |
| * | clk: keystone: add Keystone PLL clock driver | Santosh Shilimkar | 2013-10-07 | 1 | -0/+305 |
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index : op-kernel-dev | |
| Development kernel branch for OpenPOWER systems | Raptor Engineering, LLC |
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