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path: root/drivers/clk/keystone/pll.c
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* clk: keystone: fix a trivial typoGeliang Tang2015-10-191-1/+1
| | | | | | | s/regsiter/register/ Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd2015-07-281-1/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * cleanup-clk-h-includes: (62 commits) clk: Remove clk.h from clk-provider.h clk: h8300: Remove clk.h and clkdev.h includes clk: at91: Include clk.h and slab.h clk: ti: Switch clk-provider.h include to clk.h clk: pistachio: Include clk.h clk: ingenic: Include clk.h clk: si570: Include clk.h clk: moxart: Include clk.h clk: cdce925: Include clk.h clk: Include clk.h in clk.c clk: zynq: Include clk.h clk: ti: Include clk.h clk: sunxi: Include clk.h and remove unused clkdev.h includes clk: st: Include clk.h clk: qcom: Include clk.h clk: highbank: Include clk.h clk: bcm: Include clk.h clk: versatile: Remove clk.h and clkdev.h includes clk: ux500: Remove clk.h and clkdev.h includes clk: tegra: Properly include clk.h ...
| * clk: keystone: Remove clk.h includeStephen Boyd2015-07-201-1/+0
| | | | | | | | | | | | | | | | | | | | Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Remove the include here because this is a provider driver. Cc: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: keystone: make use of of_clk_parent_fill helper functionDinh Nguyen2015-07-281-2/+1
|/ | | | | | | | Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: keystone: add support for post divider register for main pllMurali Karicheri2015-06-181-2/+18
| | | | | | | | | Main PLL controller has post divider bits in a separate register in pll controller. Use the value from this register instead of fixed divider when available. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* clk: keystone: use clkod register bits for postdivMurali Karicheri2013-12-101-4/+20
| | | | | | | | | | | | | DDR3A/B, ARM and PA PLL controllers have clkod register bits for configuring postdiv values. So use it instead of using fixed post dividers for these pll controllers. Assume that if fixed-postdiv attribute is not present, use clkod register value for pistdiv. Also update the Documentation of bindings to reflect the same. Cc: Mike Turquette <mturquette@linaro.org Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* clk: keystone: add Keystone PLL clock driverSantosh Shilimkar2013-10-071-0/+305
Add the driver for the PLL IPs found on Keystone 2 devices. The PLL IP typically has a multiplier, a divider and a post-divider. The PLL IPs like ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where as the Main PLL is controlled by a PLL controller and memory map registers. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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