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path: root/drivers/clk/hisilicon
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2017-11-176-10/+18
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| * Merge branch 'clk-const' into clk-nextStephen Boyd2017-11-143-4/+4
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| | * clk: hisilicon: make clk_ops constBhumika Goyal2017-11-013-4/+4
| * | clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'Shawn Guo2017-11-141-1/+11
| * | clk: hisilicon: Delete an error message for a failed memory allocation in his...Markus Elfring2017-11-141-3/+1
| * | clk: hi3660: fix incorrect uart3 clock freqencyZhong Kaihua2017-11-141-1/+1
| * | clk: hi6220: mark clock cs_atb_syspll as criticalLeo Yan2017-11-011-1/+1
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* | License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-021-0/+1
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* clk: hi6220: change watchdog clock sourceLeo Yan2017-08-311-3/+3
* clk: hisilicon: add usb2 clocks for hi3798cv200 SoCJiancheng Xue2017-06-211-0/+21
* clk: hi6220: add acpu clockZhangfei Gao2017-06-191-0/+22
* clk: hi3660: Set PPLL2 to 2880MZhong Kaihua2017-06-191-2/+2
* clk: hi3660: add clocks for video encoder, decoder and ISPChen Jun2017-06-191-0/+40
* clk: hi3660: fix wrong parent name of clk_mux_sysbusChen Jun2017-06-191-2/+4
* clk: Hi3660: register fixed_rate_clks with CLK_OF_DECLARE_DRIVERLeo Yan2017-06-191-10/+38
* clk: hi3620: Fix a typo in one variable nameMarkus Elfring2017-04-191-3/+3
* clk: hi3620: Delete error messages for a failed memory allocation in two func...Markus Elfring2017-04-191-6/+2
* clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init()Markus Elfring2017-04-191-1/+1
* clk: hisilicon: Delete error messages for failed memory allocations in hisi_c...Markus Elfring2017-04-191-6/+4
* clk: hisilicon: Use devm_kmalloc_array() in hisi_clk_alloc()Markus Elfring2017-04-191-2/+3
* clk: hisilicon: Use kcalloc() in hisi_clk_init()Markus Elfring2017-04-191-2/+1
* clk: hi6220: add debug APB clockLeo Yan2017-04-121-0/+1
* clk: hisilicon: fix lock assignmentLeo Yan2017-01-261-0/+1
* clk: hisilicon: Add clock driver for hi3660 SoCZhangfei Gao2017-01-093-0/+575
* clk: Hi6220: enable stub clock driver for ARCH_HISILeo Yan2016-11-141-0/+1
* Merge branch 'clk-hisi' into clk-nextStephen Boyd2016-11-145-0/+719
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| * clk: hisilicon: add CRG driver for Hi3516CV300 SoCPan Wen2016-11-143-0/+339
| * clk: hisilicon: add CRG driver for Hi3798CV200 SoCJiancheng Xue2016-11-114-0/+380
* | clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock initShawn Guo2016-10-171-2/+2
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* clk: hi6220: Change syspll and media_syspll clk to 1.19GHzXinliang Liu2016-07-061-2/+2
* clk: hisilicon: hi3519: add driver remove path and fix some issuesJiancheng Xue2016-06-301-16/+100
* clk: hisilicon: add hisi_clk_unregister_* functionsJiancheng Xue2016-06-301-0/+21
* clk: hisilicon: add error processing for hisi_clk_register_* functionsJiancheng Xue2016-06-302-15/+55
* clk: hisilicon: add hisi_clk_alloc function.Jiancheng Xue2016-06-302-0/+32
* reset: hisilicon: change the definition of hisi_reset_initJiancheng Xue2016-06-303-13/+13
* Merge branch 'clk-hi6220-rtc' into clk-nextStephen Boyd2016-06-301-0/+2
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| * clk: hi6220: Add RTC clock for pl031Zhangfei Gao2016-06-301-0/+2
* | clk: hi6220: fix missing clk.h includeBen Dooks2016-06-201-0/+2
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* clk: hisilicon: add CRG driver for hi3519 socJiancheng Xue2016-05-063-0/+140
* clk: hisilicon: export some hisilicon APIs to modulesJiancheng Xue2016-05-062-15/+22
* reset: hisilicon: add reset controller driver for hisilicon SOCsJiancheng Xue2016-05-064-0/+178
* clk: hisilicon: Remove CLK_IS_ROOTStephen Boyd2016-03-025-56/+56
* clk: Remove unneeded semicolonsJavier Martinez Canillas2015-09-171-1/+1
* clk: Hi6220: separately build stub clock driverLeo Yan2015-09-032-2/+9
* clk: Hi6220: add stub clock driverLeo Yan2015-08-243-2/+278
* clk: hisi: refine parameter checking for initLeo Yan2015-08-031-8/+3
* Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd2015-07-284-8/+1
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| * clk: hisilicon: Remove clk.h includeStephen Boyd2015-07-204-8/+1
* | clk: fix some determine_rate implementationsBoris Brezillon2015-07-271-1/+1
* | clk: change clk_ops' ->determine_rate() prototypeBoris Brezillon2015-07-271-22/+17
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