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path: root/drivers/clk/hisilicon
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* clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso2014-12-031-1/+1
| | | | | | | | This is in preparation for clock providers to not have to deal with struct clk. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: hi3620: Move const initdata into correct code sectionBintian Wang2014-11-191-35/+35
| | | | | | | | Use __initconst instead of __initdata for constant init data. Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: hix5hd2: add I2C clocksWei Yan2014-09-281-0/+25
| | | | | | | | hix5hd2 add I2C clocks (I2C0~i2C5) Signed-off-by: Wei Yan <sledge.yanwei@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
* clk: hix5hd2: add watchdog0 clocksGuoxiong Yan2014-09-281-0/+5
| | | | | | | | hix5hd2 add watchdog0 clocks Signed-off-by: Guoxiong Yan <yanguoxiong@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
* clk: hix5hd2: add sd clkJiancheng Xue2014-09-281-6/+15
| | | | | | Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
* clk: hix5hd2: add complex clkZhangfei Gao2014-09-281-0/+181
| | | | | | | | Support clk of sata, usb and ethernet Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
* clk: hisi: add clk-hix5hd2.cZhangfei Gao2014-05-122-0/+102
| | | | | | Signed-off-by: Haifeng Yan <haifeng.yan@linaro.org> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
* clk: hisi: add hisi_clk_register_gateZhangfei Gao2014-05-122-0/+30
| | | | | | | Add hisi_clk_register_gate register clk gate table Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
* clk: hisi: use clk_register_mux_table in hisi_clk_register_muxZhangfei Gao2014-05-122-5/+9
| | | | | | | Platform hix5hd2 use mux table, so use clk_register_mux_table instead Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
* clk: hisilicon: fix warning from smatchZhangfei Gao2014-03-201-8/+7
| | | | | | | | | drivers/clk/hisilicon/clk-hi3620.c:338 mmc_clk_delay() warn: always true condition '(para >= 0) => (0-u32max >= 0)' Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Merge tag 'clk-hisi' of ↵Mike Turquette2014-03-195-39/+128
|\ | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilcon updating clock drivers for Hisilicon
| * clk: hisi: remove static variableHaojian Zhuang2014-03-194-42/+72
| | | | | | | | | | | | | | Remove the static variable. So these common clock register helper could be used in more SoCs. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| * clk: hip04: add clock driverHaojian Zhuang2014-03-192-1/+58
| | | | | | | | | | | | Now only fixed rate clocks are appended into the clock driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| * clk: hisi: assign missing clk to tableHaojian Zhuang2014-03-191-0/+2
| | | | | | | | | | | | The fixed rate and fixed factor clock isn't registered to clk table. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
* | clk: hisilicon: add hi3620_mmc_clksZhangfei Gao2014-02-261-0/+274
|/ | | | | | | | | | | Suggest by Arnd: abstract mmc tuning as clock behavior, also because different soc have different tuning method and registers. hi3620_mmc_clks is added to handle mmc clock specifically on hi3620. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: hi3620: add gate clock flagHaojian Zhuang2013-12-111-59/+59
| | | | | | Add missing CLK_SET_RATE_PARENT flag for gate clock. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
* clk: hi3620: fix wrong flags on dividerHaojian Zhuang2013-12-111-11/+11
| | | | | | | The flags on dividers should be CLK_DIVIDER_HIWORD_MASK, not CLK_MUX_HIWORD_MASK. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
* clk: hisilicon: add common clock supportHaojian Zhuang2013-12-045-0/+651
Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is used to support the clock gate that enable/disable/status registers are seperated. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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