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path: root/drivers/clk/clk-qoriq.c
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* clk: qoriq: Add ls1043a support.Hou Zhiqiang2015-10-271-0/+38
| | | | | | Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
* clk: qoriq: Fix wrong data in p2041_cmux_grp2Scott Wood2015-10-221-2/+2
| | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
* clk: qoriq: Add ls2080a support.Scott Wood2015-10-211-9/+68
| | | | | | | | | LS2080A is the first implementation of the chassis 3 clockgen, which has a different register layout than previous chips. It is also little endian, unlike previous chips. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qoriq: Move chip-specific knowledge into driverScott Wood2015-10-211-221/+1040
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree should describe the chips (or chip-like subblocks) in the system, but it generally does not describe individual registers -- it should identify, rather than describe, a programming interface. This has not been the case with the QorIQ clockgen nodes. The knowledge of what each bit setting of CLKCnCSR means is encoded in three places (binding, pll node, and mux node), and the last also needs to know which options are valid on a particular chip. All three of these locations are considered stable ABI, making it difficult to fix mistakes (of which I have found several), much less refactor the abstraction to be able to address problems, limitations, or new chips. Under the current binding, a pll clock specifier of 2 means that the PLL is divided by 4 -- and the driver implements this, unless there happen to be four clock-output-names rather than 3, in which case it interprets it as PLL divided by 3. This does not appear in the binding documentation at all. That hack is now considered stable ABI. The current device tree nodes contain errors, such as saying that T1040 can set a core clock to PLL/4 when only PLL and PLL/2 are options. The current binding also ignores some restrictions on clock selection, such as p5020's requirement that if a core uses the "wrong" PLL, that PLL must be clocked lower than the "correct" PLL and be at most 80% of the rated CPU frequency. Possibly because of the lack of the ability to express such nuance in the binding, some valid options are omitted from the device trees, such as the ability on p4080 to run cores 0-3 from PLL3 and cores 4-7 from PLL1 (again, only if they are at most 80% of rated CPU frequency). This omission, combined with excessive caution in the cpufreq driver (addressed in a subsequent patch), means that currently on a 1500 MHz p4080 with typical PLL configuration, cpufreq can lower the frequency to 1200 MHz on half the CPUs and do nothing on the others. With this patchset, all CPUs can be lowered to 1200 MHz on a rev2 p4080, and on a rev3 p4080 half can be lowered to 750 MHz and the other half to 600 MHz. The current binding only deals with CPU clocks. To describe FMan in the device tree, we need to describe its clock. Some chips have additional muxes that work like the CPU muxes, but are not described in the device tree. Others require inspecting the Reset Control Word to determine which PLL is used. Rather than continue to extend this mess, replace it. Have the driver bind to the chip-specific clockgen compatible, and keep the detailed description of quirky chip variations in the driver, where it can be easily fixed, refactored, and extended. Older device trees will continue to work (including a workaround for old ls1021a device trees that are missing compatible and reg in the clockgen node, which even the old binding required). The pll/mux details in old device trees will be ignored, but "clocks" properties pointing at the old nodes will still work, and be directed at the corresponding new clock. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qoriq: Add support for the platform PLLEmil Medve2015-02-181-0/+83
| | | | | | | Change-Id: Iac11ed95f274485a86d2c11f32a3dc502bcd020f Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Acked-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qoriq: Use pr_fmt()Emil Medve2015-01-281-2/+5
| | | | | | | Currently a mix of clk-qoriq/qoriq-clk and no prefix is used Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qoriq: Replace kzalloc() with kmalloc()Emil Medve2015-01-281-1/+1
| | | | | | | Where the memset() is not necessary Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qoriq: Make local symbol 'static'Emil Medve2015-01-281-1/+1
| | | | | | | drivers/clk/clk-qoriq.c:59:22: warning: symbol 'cmux_ops' was not declared. Should it be static? Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qoriq: Fix checkpatch type OOM_MESSAGEEmil Medve2015-01-281-12/+5
| | | | | | | | | | | | | | | | | | | | | WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!parent_names) { + pr_err("%s: could not allocate parent_names\n", __func__); WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!cmux_clk) { + pr_err("%s: could not allocate cmux_clk\n", __func__); WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!subclks) { + pr_err("%s: could not allocate subclks\n", __func__); WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!onecell_data) { + pr_err("%s: could not allocate onecell_data\n", __func__); Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qoriq: Fix checkpatch type ALLOC_SIZEOF_STRUCTEmil Medve2015-01-281-2/+2
| | | | | | | | | | | CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*cmux_clk)...) over kzalloc(sizeof(struct cmux_clk)...) + cmux_clk = kzalloc(sizeof(struct cmux_clk), GFP_KERNEL); CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*onecell_data)...) over kzalloc(sizeof(struct clk_onecell_data)...) + onecell_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qoriq: Fix checkpatch type ALLOC_WITH_MULTIPLYEmil Medve2015-01-281-2/+2
| | | | | | | | WARNING:ALLOC_WITH_MULTIPLY: Prefer kcalloc over kzalloc with multiply + subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL); Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qoriq: Fix checkpatch type PARENTHESIS_ALIGNMENTEmil Medve2015-01-281-4/+4
| | | | | | | | | | | | | | | | | | | | | CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + rc = of_property_read_string_index(np, "clock-output-names", + 0, &clk_name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + pr_err("Could not register clock provider for node:%s\n", + np->name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + rc = of_property_read_string_index(np, "clock-output-names", + i, &clk_name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + pr_err("Could not register clk provider for node:%s\n", + np->name); Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: ppc-corenet: rename driver to clk-qoriqTang Yuantian2015-01-201-0/+283
Freescale introduced new ARM-based socs which using the compatible clock IP block with PowerPC-based socs'. So this driver can be used on both platforms. Updated relevant descriptions and renamed this driver to better represent its meaning and keep the function of driver untouched. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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