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* agp: iommu_gfx_mapped only available if CONFIG_INTEL_IOMMU is setKeith Packard2011-11-081-2/+3
| | | | | | | | | | | Kernels with no iommu support cannot ever need the Ironlake work-around, so never enable it in that case. Might be better to completely remove the work-around from the kernel in this case? Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* drm/i915: fix if statement (bogus semi-colon)Dan Carpenter2011-11-081-1/+1
| | | | | | | | The semi-colon is a typo here and it makes the if statement unconditional. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* Merge branch 'misc-3.2' of ↵Linus Torvalds2011-11-021-2/+4
|\ | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux * 'misc-3.2' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux: MAINTAINERS: Update entry for IA64 [IA64] gpio: GENERIC_GPIO default must be n [IA64[ add CONFIG_NET_VENDOR_INTEL=y to default config files where needed [IA64] agp/hp-agp: Allow binding user memory to the AGP GART [IA64] sn2: add missing put_cpu()
| * [IA64] agp/hp-agp: Allow binding user memory to the AGP GARTÉmeric Maschino2011-08-231-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dmesg reports: [   29.365973] [TTM] AGP Bind memory failed. [   29.366015] radeon 0000:80:00.0: object_init failed for (4096, 0x00000002) [   29.366052] radeon 0000:80:00.0: (-22) create WB bo failed [   29.366087] radeon 0000:80:00.0: Disabling GPU acceleration [   29.366124] [drm] radeon: cp finalized [   29.366168] [drm] radeon: cp finalized [   29.366210] [TTM] Finalizing pool allocator. [   29.366924] [TTM] Zone  kernel: Used memory at exit: 0 kiB. [   29.366961] [TTM] Zone   dma32: Used memory at exit: 0 kiB. [   29.366996] [drm] radeon: ttm finalized [   29.367030] [drm] Forcing AGP to PCI mode This patch allows binding user memory to the AGP GART on zx1-based systems. dmesg thus no more complains about AGP bind memory failure, disabled GPU acceleration or AGP mode forced to PCI. Original work from Francisco Jerez in agp/amd-k7 (https://lkml.org/lkml/2010/10/15/469). Tested-by: Émeric Maschino <emeric.maschino@gmail.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | Merge branch 'drm-core-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds2011-10-281-0/+28
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'drm-core-next' of git://people.freedesktop.org/~airlied/linux: (290 commits) Revert "drm/ttm: add a way to bo_wait for either the last read or last write" Revert "drm/radeon/kms: add a new gem_wait ioctl with read/write flags" vmwgfx: Don't pass unused arguments to do_dirty functions vmwgfx: Emulate depth 32 framebuffers drm/radeon: Lower the severity of the radeon lockup messages. drm/i915/dp: Fix eDP on PCH DP on CPT/PPT drm/i915/dp: Introduce is_cpu_edp() drm/i915: use correct SPD type value drm/i915: fix ILK+ infoframe support drm/i915: add DP test request handling drm/i915: read full receiver capability field during DP hot plug drm/i915/dp: Remove eDP special cases from bandwidth checks drm/i915/dp: Fix the math in intel_dp_link_required drm/i915/panel: Always record the backlight level again (but cleverly) i915: Move i915_read/write out of line drm/i915: remove transcoder PLL mashing from mode_set per specs drm/i915: if transcoder disable fails, say which drm/i915: set watermarks for third pipe on IVB drm/i915: export a CPT mode set verification function drm/i915: fix transcoder PLL select masking ...
| * | drm/i915: ILK + VT-d workaroundBen Widawsky2011-10-201-0/+28
| |/ | | | | | | | | | | | | | | | | | | | | Idle the GPU before doing any unmaps. We know if VT-d is in use through an exported variable from iommu code. This should avoid a known HW issue. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Keith Packard <keithp@keithp.com>
* | Merge branch 'core-iommu-for-linus' of ↵Linus Torvalds2011-10-261-2/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip * 'core-iommu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86, ioapic: Consolidate the explicit EOI code x86, ioapic: Restore the mask bit correctly in eoi_ioapic_irq() x86, kdump, ioapic: Reset remote-IRR in clear_IO_APIC iommu: Rename the DMAR and INTR_REMAP config options x86, ioapic: Define irq_remap_modify_chip_defaults() x86, msi, intr-remap: Use the ioapic set affinity routine iommu: Cleanup ifdefs in detect_intel_iommu() iommu: No need to set dmar_disabled in check_zero_address() iommu: Move IOMMU specific code to intel-iommu.c intr_remap: Call dmar_dev_scope_init() explicitly x86, x2apic: Enable the bios request for x2apic optout
| * | iommu: Rename the DMAR and INTR_REMAP config optionsSuresh Siddha2011-09-211-2/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the CONFIG_DMAR to CONFIG_INTEL_IOMMU to be consistent with the other IOMMU options. Rename the CONFIG_INTR_REMAP to CONFIG_IRQ_REMAP to match the irq subsystem name. And define the CONFIG_DMAR_TABLE for the common ACPI DMAR routines shared by both CONFIG_INTEL_IOMMU and CONFIG_IRQ_REMAP. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: yinghai@kernel.org Cc: youquan.song@intel.com Cc: joerg.roedel@amd.com Cc: tony.luck@intel.com Cc: dwmw2@infradead.org Link: http://lkml.kernel.org/r/20110824001456.558630224@sbsiddha-desk.sc.intel.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | char: Convert vmalloc/memset to vzallocJoe Perches2011-09-151-2/+1
|/ | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* agp/intel: Fix typo in G4x_GMCH_SIZE_VT_2MChris Wilson2011-07-131-3/+4
| | | | | | | | | | | | Konstantin Belousov found an error in the define of G4x_GMCH_SIZE_VT_2M relative to the GMCH specs, and confirmed that indeed one of his users with a Q45 reports 0xb not 0xc for a 2/2MiB GATT. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Konstantin Belousov <kostikbel@gmail.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
* agp/uninorth: Fix lockups with radeon KMS and >1x.Michel Dänzer2011-05-221-1/+1
| | | | | | | | | | | | | | | | | | | This was based on a description by Ben Herrenschmidt: > I've removed that SBA reset from the normal TLB invalidation path and > left it only once after turning AGP on. About six months ago, he said: > I did it a bit differently, but yeah, you get the idea. I'm doing a > patch series so don't bother pushing things too hard yet. But I haven't seen anything from him about this since then, and people are regularly hitting these lockups, so here we are... Signed-off-by: Michel Dänzer <daenzer@vmware.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Dave Airlie <airlied@gmail.com>
* agp/intel: add Ivy Bridge supportJesse Barnes2011-05-133-0/+21
| | | | | | | | Just use the Sandy Bridge routines. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* agp: fix arbitrary kernel memory writesVasiliy Kulikov2011-04-211-3/+8
| | | | | | | | | | | | pg_start is copied from userspace on AGPIOC_BIND and AGPIOC_UNBIND ioctl cmds of agp_ioctl() and passed to agpioc_bind_wrap(). As said in the comment, (pg_start + mem->page_count) may wrap in case of AGPIOC_BIND, and it is not checked at all in case of AGPIOC_UNBIND. As a result, user with sufficient privileges (usually "video" group) may generate either local DoS or privilege escalation. Signed-off-by: Vasiliy Kulikov <segoon@openwall.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* agp: fix OOM and buffer overflowVasiliy Kulikov2011-04-211-1/+7
| | | | | | | | | | | | | | | | | | | page_count is copied from userspace. agp_allocate_memory() tries to check whether this number is too big, but doesn't take into account the wrap case. Also agp_create_user_memory() doesn't check whether alloc_size is calculated from num_agp_pages variable without overflow. This may lead to allocation of too small buffer with following buffer overflow. Another problem in agp code is not addressed in the patch - kernel memory exhaustion (AGPIOC_RESERVE and AGPIOC_ALLOCATE ioctls). It is not checked whether requested pid is a pid of the caller (no check in agpioc_reserve_wrap()). Each allocation is limited to 16KB, though, there is no per-process limit. This might lead to OOM situation, which is not even solved in case of the caller death by OOM killer - the memory is allocated for another (faked) process. Signed-off-by: Vasiliy Kulikov <segoon@openwall.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* Fix common misspellingsLucas De Marchi2011-03-314-4/+4
| | | | | | Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
* Merge branch 'drm-intel-fixes' of ↵Dave Airlie2011-02-242-35/+22
|\ | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel into drm-fixes * 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel: drm/i915: fix corruptions on i8xx due to relaxed fencing drm/i915: skip FDI & PCH enabling for DP_A agp/intel: Experiment with a 855GM GWB bit drm/i915: don't enable FDI & transcoder interrupts after all drm/i915: Ignore a hung GPU when flushing the framebuffer prior to a switch
| * agp/intel: Experiment with a 855GM GWB bitChris Wilson2011-02-222-35/+22
| | | | | | | | | | | | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27187 Tested-by: Thorsten Vollmer <thorsten@thvo.de> (DFI-ACP G5M150-N w/852GME) Tested-by: Moritz Brunner <2points@gmx.org> (Asus M2400N/i855GM) Tested-by: Indan Zupancic <indan@nul.nu> (Thinkpad X40/855GM rev 02) Tested-by: Eric Anholt <eric@anholt.net> (865G) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | amd64-agp: fix crash at second module loadFlorian Mickler2011-02-231-2/+7
|/ | | | | | | | | | | The module forgot to sometimes unregister some resources. This fixes Bug #22882. [Patch updated to 2.6.38-rc3 by Randy Dunlap.] Tested-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Florian Mickler <florian@mickler.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
* agp: ensure GART has an address before enabling itStephen Kitt2011-02-041-11/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some BIOSs (eg. the AMI BIOS on the Asus P4P800 motherboard) don't initialise the GART address, and pcibios_assign_resources() can ignore it because it can be marked as a host bridge (see https://bugzilla.kernel.org/show_bug.cgi?id=24392#c5 for details). This was handled correctly up to 2.6.35, but the pci_enable_device() cleanup in 2.6.36 96576a9e1a0cdb8 ("agp: intel-agp: do not use PCI resources before pci_enable_device()") means that the kernel tries to enable the GART before assigning it an address; in such cases the GART overlaps with other device assignments and ends up being disabled. This patch fixes https://bugzilla.kernel.org/show_bug.cgi?id=24392 Note that I imagine efficeon-agp.c probably has the same problem, but I can't test that and I'd like to make sure this patch is suitable for -stable (since 2.6.36 and 2.6.37 are affected). Signed-off-by: Stephen Kitt <steve@sk2.org> Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: Maciej Rutecki <maciej.rutecki@gmail.com> Cc: "Rafael J. Wysocki" <rjw@sisk.pl> Cc: Kulikov Vasiliy <segooon@gmail.com> Cc: Florian Mickler <florian@mickler.org> Cc: <stable@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
* Revert "agp: AMD AGP is used on UP1100 & UP1500 alpha boxen"Matt Turner2011-02-041-1/+1
| | | | | | | | | | | | | | | | | | | | This reverts commit f191f144079b0083c6fa7d01a4acbd7263fb5032. The AMD 751 and 761 chipsets are used on the UP1000, UP1100, and UP1500 OEM motherboards, but they neglect to do anything to make AGP work. According to Ivan Kokshaysky: There is quite fundamental conflict between the Alpha architecture and x86 AGP implementation - Alpha is entirely cache coherent by design, while x86 AGP is not (I mean native AGP DMA transactions, not a PCI over AGP). There are no such things as non-cacheable mappings or software support for cache flushing/invalidation on Alpha, so x86 AGP code won't work on Nautilus. So there's no point in allowing this driver to be configured on Alpha. Signed-off-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* amd-k7-agp: remove non-x86 codeMatt Turner2011-02-041-19/+0
| | | | | | | | amd-k7-agp can't be built on Alpha anymore, so remove now unnecessary code. Signed-off-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/i915,agp/intel: Do not clear stolen entriesChris Wilson2011-01-241-10/+9
| | | | | | | | | | | | | We can only utilize the stolen portion of the GTT if we are in sole charge of the hardware. This is only true if using GEM and KMS, otherwise VESA continues to access stolen memory. Reported-by: Arnd Bergmann <arnd@arndb.de> Reported-by: Frederic Weisbecker <fweisbec@gmail.com> Tested-by: Jiri Olsa <jolsa@redhat.com> Tested-by: Frederic Weisbecker <fweisbec@gmail.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* agp/intel: Fix device names of i845 and 845GOswald Buddenhagen2011-01-142-3/+3
| | | | | | | | They got mixed up when the switch was converted to a table in 2007. Signed-off-by: Oswald Buddenhagen <ossi@kde.org> [ickle: minor changes for 2.6.37+] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* i915/gtt: fix ordering causing DMAR errors on object teardown.Dave Airlie2011-01-121-2/+2
| | | | | | | | | | | Previous to the last GTT rework we always rewrote the GTT then unmapped the object, somehow this got reversed in the rework in 2.6.37-rc5 timeframe. This fix needs to go to stable in an alternate form since the code changed. This fixes DMAR reports on my Ironlake HP2540p. Signed-off-by: Dave Airlie <airlied@redhat.com>
* i915/gtt: fix ordering issues with status setup and DMARDave Airlie2011-01-121-2/+2
| | | | | | | | This code was setting up the status page before setting the DMAR-is-on-bit, so we were getting DMAR errors on the status page. Reverse the two bits of init code to the correct result. Signed-off-by: Dave Airlie <airlied@redhat.com>
* agp/intel: Flush the chipset write buffers when changing GTT baseChris Wilson2011-01-112-0/+11
| | | | | | | | | | Flush the chipset write buffers before and after adjusting the GTT base register, just in case. We only modify this value upon initialisation (boot and resume) so there should be no outstanding writes, however there are always those persistent PGTBL_ER that keep getting reported upon resume. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* Merge branch 'drm-core-next' of ↵Linus Torvalds2011-01-108-472/+363
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (390 commits) drm/radeon/kms: disable underscan by default drm/radeon/kms: only enable hdmi features if the monitor supports audio drm: Restore the old_fb upon modeset failure drm/nouveau: fix hwmon device binding radeon: consolidate asic-specific function decls for pre-r600 vga_switcheroo: comparing too few characters in strncmp() drm/radeon/kms: add NI pci ids drm/radeon/kms: don't enable pcie gen2 on NI yet drm/radeon/kms: add radeon_asic struct for NI asics drm/radeon/kms/ni: load default sclk/mclk/vddc at pm init drm/radeon/kms: add ucode loader for NI drm/radeon/kms: add support for DCE5 display LUTs drm/radeon/kms: add ni_reg.h drm/radeon/kms: add bo blit support for NI drm/radeon/kms: always use writeback/events for fences on NI drm/radeon/kms: adjust default clock/vddc tracking for pm on DCE5 drm/radeon/kms: add backend map workaround for barts drm/radeon/kms: fill gpu init for NI asics drm/radeon/kms: add disabled vbios accessor for NI asics drm/radeon/kms: handle NI thermal controller ...
| * Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-12-141-2/+9
| |\
| * \ Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-12-051-2/+4
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Immediate merge for the conflicting introduction of HAS_COHERENT_RINGS. Conflicts: drivers/gpu/drm/i915/i915_dma.c include/drm/i915_drm.h
| * | | agp/intel: Remove duplicate constChris Wilson2010-11-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | drivers/char/agp/intel-gtt.c:340:48: warning: duplicate const Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | intel-gtt: export api for drm/i915Daniel Vetter2010-11-231-52/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just some minor shuffling to get rid of any agp traces in the exported functions. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | agp: kill agp_rebind_memoryDaniel Vetter2010-11-231-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Its only user, intel-gtt.c is now gone. Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: restore gtt on resume in the drm instead of in intel-gtt.koDaniel Vetter2010-11-231-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This still uses the agp functions to actually reinstate the mappings (with a gross hack to make agp cooperate), but it wires everything up correctly for the switchover. The call to agp_rebind_memory can be dropped because all non-kms drivers do all their rebinding on EnterVT. v2: Be more paranoid and flush the chipset cache after restoring gtt mappings. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | agp: kill agp_flush_chipset and corresponding ioctlDaniel Vetter2010-11-236-24/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The intel drm calls the chipset functions now directly. Userspace never called the corresponding ioctl, hence it can be killed, too. Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915/gtt: call chipset flush directlyDaniel Vetter2010-11-231-0/+7
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915|intel-gtt: consolidate intel-gtt.h headersDaniel Vetter2010-11-231-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ... and a few other defines. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | intel-gtt: fold i81x-only dcache support into the generic driverDaniel Vetter2010-11-231-89/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now the intel-gtt.c rewrite is complete! Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | intel-gtt: switch i81x to the common initialization helpersDaniel Vetter2010-11-231-127/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Still a separate agp_bridge_driver because of the i81x-only dedicated vram support. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | intel-gtt: switch i81x to the write_entry helpersDaniel Vetter2010-11-231-92/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialization is still done with the old code with a few added things sprinkled in to make the intel_fake_agp helper functions work. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | intel-gtt: kill unneeded sandybridge memory typesDaniel Vetter2010-11-231-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Used for the now dead agp type_to_mask stuff. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | intel-gtt: drop dcache support for i830 and laterDaniel Vetter2010-11-231-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i830_check_flags already disallows it, so no need to implement it in the write_entry function. Seems to be a remnant from i810 support. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | agp/intel: Remove confusion of stolen entries not stolen memoryChris Wilson2010-11-231-33/+7
| | | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | agp/intel: Remove the artificial cap on stolen sizeChris Wilson2010-11-231-13/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the stolen memory does not also steal entries from the GTT, we can use all the memory the BIOS set aside for the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-11-221-1/+0
| |\ \ \ | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/gpu/drm/i915/i915_gem.c
| * \ \ \ Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-11-151-0/+5
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/gpu/drm/i915/i915_gem.c drivers/gpu/drm/i915/intel_ringbuffer.c
| * | | | | agp/intel: restore cache behavior on sandybridgeZhenyu Wang2010-11-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This restores cache behavior for default AGP_USER_MEMORY as uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only. I've seen different cache behavior on one sandybridge desktop CPU vs. another mobile CPU. Until we figure out how to detect the real cache config, restore back to the original behavior now. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | | | agp/intel: fix cache control for sandybridgeZhenyu Wang2010-11-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | | | agp/intel: the GMCH is always enabled for integrated processor graphicsChris Wilson2010-10-311-16/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... and trying to set the bit is ineffectual. Fixes the regression from e380f60 which detected that we were trying to do undefined operations on the I830_GMCH_CTRL. Reported-by: Alexey Fisher <bug-track@fisher-privat.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | | | agp/intel: Sandybridge doesn't require GMCH enablingChris Wilson2010-10-291-7/+30
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | | | intel-gtt: maximize ggtt size on platforms that support thisDaniel Vetter2010-10-272-29/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On VT-d supporting platforms the GGTT is allocated in a stolen mem section separate from graphcis stolen mem. The GMCH register contains a bitfield specifying the size of that region. Docs suggest that this region can only be used for GGTT and PPGTT. Hence ensure that the PPGTT is disabled and use the complete area for the GGTT. Unfortunately the graphics core on G33/Pineview can't cope with really large GTTs and the BIOS usually enables the maximum of 512MB. So don't bother with maximizing the GTT on these platforms. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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