summaryrefslogtreecommitdiffstats
path: root/arch
Commit message (Collapse)AuthorAgeFilesLines
* missing argument in bin_attribute ->read()/->write()Al Viro2007-07-151-5/+5
| | | | | | | | Fallout from commit 91a6902958f052358899f58683d44e36228d85c2 ('sysfs: add parameter "struct bin_attribute *" ...') Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* pass -msize-long to sparse on s390Al Viro2007-07-151-1/+1
| | | | | | | | s390 is the only 32bit with unsigned long for size_t (usual for those is unsigned int). Tell sparse... Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* the wrong variable checked after request_irq()Al Viro2007-07-151-1/+1
| | | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreqLinus Torvalds2007-07-135-291/+45
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreq: [CPUFREQ] Fix typos in powernow-k8 printk's. [CPUFREQ] Restore previously used governor on a hot-replugged CPU [CPUFREQ] bugfix cpufreq in combination with performance governor [CPUFREQ] powernow-k8 compile fix. [CPUFREQ] the overdue removal of X86_SPEEDSTEP_CENTRINO_ACPI [CPUFREQ] Longhaul - Option to disable ACPI C3 support Fixed up arch/i386/kernel/cpu/cpufreq/powernow-k8.c due to revert that got fixed differently in the cpufreq branch. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * [CPUFREQ] Fix typos in powernow-k8 printk's.Dave Jones2007-07-131-8/+11
| | | | | | | | | | | | | | | | | | | | Based on a patch from Joachim which didn't apply, so I fixed it up by hand, and also corrected the surrounding indentation a little. Signed-off-by: Joachim.Deguara <joachim.deguara@amd.com> Acked-by: Mark Langsdorf <mark.langsdorf@amd.com> Signed-off-by: Dave Jones <davej@redhat.com>
| * [CPUFREQ] powernow-k8 compile fix.Andrew Morton2007-07-131-1/+6
| | | | | | | | | | | | | | Make it compile on UP. Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dave Jones <davej@redhat.com>
| * [CPUFREQ] the overdue removal of X86_SPEEDSTEP_CENTRINO_ACPIAdrian Bunk2007-07-133-281/+19
| | | | | | | | | | | | | | | | This patch contains the overdue removal of X86_SPEEDSTEP_CENTRINO_ACPI. Signed-off-by: Adrian Bunk <bunk@stusta.de> Acked-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Dave Jones <davej@redhat.com>
| * [CPUFREQ] Longhaul - Option to disable ACPI C3 supportRafał Bilski2007-07-131-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | On some motherboards ACPI C3 is available, but it isn't causing frequency transition on VIA Nehemiah. Longhaul wasn't working at all earlier, but due to scaling_cur_speed returning true CPU frequency now, it looks like CPU is getting stuck at highest frequency since 2.6.21. I didn't find a reason. Halt is causing frequency transition. Signed-off-by: Rafal Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
* | Merge branch 'ioat-md-accel-for-linus' of ↵Linus Torvalds2007-07-1310-3/+445
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://lost.foo-projects.org/~dwillia2/git/iop * 'ioat-md-accel-for-linus' of git://lost.foo-projects.org/~dwillia2/git/iop: (28 commits) ioatdma: add the unisys "i/oat" pci vendor/device id ARM: Add drivers/dma to arch/arm/Kconfig iop3xx: surface the iop3xx DMA and AAU units to the iop-adma driver iop13xx: surface the iop13xx adma units to the iop-adma driver dmaengine: driver for the iop32x, iop33x, and iop13xx raid engines md: remove raid5 compute_block and compute_parity5 md: handle_stripe5 - request io processing in raid5_run_ops md: handle_stripe5 - add request/completion logic for async expand ops md: handle_stripe5 - add request/completion logic for async read ops md: handle_stripe5 - add request/completion logic for async check ops md: handle_stripe5 - add request/completion logic for async compute ops md: handle_stripe5 - add request/completion logic for async write ops md: common infrastructure for running operations with raid5_run_ops md: raid5_run_ops - run stripe operations outside sh->lock raid5: replace custom debug PRINTKs with standard pr_debug raid5: refactor handle_stripe5 and handle_stripe6 (v3) async_tx: add the async_tx api xor: make 'xor_blocks' a library routine for use with async_tx dmaengine: make clients responsible for managing channels dmaengine: refactor dmaengine around dma_async_tx_descriptor ...
| * | ARM: Add drivers/dma to arch/arm/KconfigDan Williams2007-07-131-0/+2
| | | | | | | | | | | | | | | Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | iop3xx: surface the iop3xx DMA and AAU units to the iop-adma driverDan Williams2007-07-138-0/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the platform device definitions and the architecture specific support routines (i.e. register initialization and descriptor formats) for the iop-adma driver. Changelog: * add support for > 1k zero sum buffer sizes * added dma/aau platform devices to iq80321 and iq80332 setup * fixed the calculation in iop_desc_is_aligned * support xor buffer sizes larger than 16MB * fix places where software descriptors are assumed to be contiguous, only hardware descriptors are contiguous for up to a PAGE_SIZE buffer size * convert to async_tx * add interrupt support * add platform devices for 80219 boards * do not call platform register macros in driver code * remove switch() statements for compatible register offsets/layouts * change over to bitmap based capabilities * remove unnecessary ARM assembly statement * checkpatch.pl fixes * gpl v2 only correction * phys move to dma_async_tx_descriptor Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | iop13xx: surface the iop13xx adma units to the iop-adma driverDan Williams2007-07-131-3/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the platform device definitions and the architecture specific support routines (i.e. register initialization and descriptor formats) for the iop-adma driver. Changelog: * added 'descriptor pool size' to the platform data * add base support for buffer sizes larger than 16MB (hw max) * build error fix from Kirill A. Shutemov * rebase for async_tx changes * add interrupt support * do not call platform register macros in driver code * remove unnecessary ARM assembly statement * checkpatch.pl fixes * gpl v2 only correction Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | | Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2007-07-138-84/+23
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Workaround for a sparse warning in include/asm-mips/mach-tx4927/ioremap.h [MIPS] Make show_code static and add __user tag [MIPS] Workaround for a sparse warning in include/asm-mips/compat.h [MIPS] Add some __user tags [MIPS] math-emu minor cleanup [MIPS] Kill CONFIG_TX4927BUG_WORKAROUND [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_FB_XPERT98 [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1000_SRC_CLK [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1000_USE32K [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1XXX_PSC_SPI [CHAR] Delete leftovers of old Alchemy UART driver
| * | | [MIPS] Make show_code static and add __user tagAtsushi Nemoto2007-07-131-3/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | [MIPS] Add some __user tagsAtsushi Nemoto2007-07-133-9/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | [MIPS] math-emu minor cleanupAtsushi Nemoto2007-07-131-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Declaring emulpc and contpc as "unsigned long" can get rid of some casts. This also get rid of some sparse warnings. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | [MIPS] Kill CONFIG_TX4927BUG_WORKAROUNDAtsushi Nemoto2007-07-131-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Kill workarounds for very early chip (perhaps pre-TX4927A). Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_FB_XPERT98Ralf Baechle2007-07-131-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | Noticed by Robert P. J. Day (rpjday@mindspring.com). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1000_SRC_CLKRalf Baechle2007-07-131-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | Noticed by Robert P. J. Day (rpjday@mindspring.com). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1000_USE32KRalf Baechle2007-07-131-25/+0
| | | | | | | | | | | | | | | | | | | | | | | | Noticed by Robert P. J. Day (rpjday@mindspring.com). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1XXX_PSC_SPIRalf Baechle2007-07-131-8/+1
| | |/ | |/| | | | | | | | | | | | | Noticed by Robert P. J. Day (rpjday@mindspring.com). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | Revert "[CPUFREQ] powernow-k8: clarify number of cores."Linus Torvalds2007-07-131-3/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 904f7a3f042b5c6aa9e53ce83f2c9de5e33170ff. As noted by Peter Anvin: "It causes build failures on i386. Yet another case of unnecessary divergence between i386 and x86-64 I'm afraid..." Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2007-07-1258-371/+2530
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (50 commits) [ARM] sa1100: remove boot time RTC initialisation [ARM] sa1100: stop doing our own rtc management over suspend [ARM] 4474/1: Do not check the PSR_F_BIT in valid_user_regs [ARM] 4473/2: Take the HWCAP definitions out of the elf.h file [ARM] pxa: move platform devices to separate header file [ARM] pxa: move device registration into CPU-specific file [ARM] pxa: remove boot time RTC initialisation [ARM] pxa: stop doing our own rtc management over suspend [ARM] 4451/1: pxa: make dma.c generic and remove cpu specific dma code [ARM] 4450/1: pxa: add pxa25x_init_irq() and pxa27x_init_irq() [ARM] 4440/1: PXA: enable the checking of ICIP2 for IRQs [ARM] 4438/1: PXA: remove #ifdef .. #endif from pxa_gpio_demux_handler() [ARM] 4437/1: PXA: move the GPIO IRQ initialization code to pxa_init_irq_gpio() [ARM] 4436/1: PXA: move low IRQ initialization code to pxa_init_irq_low() [ARM] 4435/1: PXA: remove PXA_INTERNAL_IRQS [ARM] 4434/1: PXA: remove PXA_IRQ_SKIP [ARM] pxa: Fix PXA27x suspend type validation, remove pxa_pm_prepare() [ARM] pxa: move pm_ops structure into CPU specific files [ARM] pxa: introduce cpu_is_pxaXXX macros [ARM] pxa: remove MMC register defines from pxa-regs.h ...
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| *-------------. \ Merge branches 'at91', 'davinci', 'imx', 'iop', 'ixp', 'ks8695', 'misc', ↵Russell King2007-07-1256-371/+2336
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'pxa' and 's3c' into devel
| | | | | | | | | * | [ARM] 4470/2: OSIRIS: large page NAND supportBen Dooks2007-07-121-3/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the partition layout on the revision B modules which have large page NAND fitted. The new partition table accounts for the use of the 128KiB block parts, which means the second partition on the device is moved to the new boundary. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | | * | [ARM] 4467/3: BAST: AX88796 device resourcesBen Dooks2007-07-121-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add resources for the AX88796 on the Simtec BAST. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | | * | [ARM] 4469/1: ANUBIS: large page NAND supportBen Dooks2007-07-121-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the partition layour used on the revision B modules which ship with large page NAND flash as default. The differnce between the old and new layouts is that the large page devices use 128KiB blocks, so the initial loader partition now ends at 128KiB boundary pushing the begining of partition 1 up. The rest of the partitions are in the same place as the small page NAND devices. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | | * | [ARM] 4468/2: ANUBIS: Add SM501 device resourcesBen Dooks2007-07-121-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add resources for the SM501 present on the Simtec Anubis board, including the framebuffer and the I2C for DDC. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | | * | [ARM] 4466/1: ANUBIS: Anubis AX88796 supportBen Dooks2007-07-121-0/+35
| | | | | | | | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the resources necessary for the AX88796 driver to attach to the AX88796 network controller fitted on the Simtec Anubis board. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] pxa: move platform devices to separate header fileRussell King2007-07-1214-12/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] pxa: move device registration into CPU-specific fileRussell King2007-07-124-76/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows individual CPU support to determine which platform devices should be registered. Also fix a copy-n-paste bug in the I2C power platform device entry. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] pxa: remove boot time RTC initialisationRussell King2007-07-121-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RTC library code contains everything necessary to set the system time from the RTC; for similar reasons as the previous commit, it's far better to let the RTC library code sort this out rather than implement something which might not be appropriate for everyone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] pxa: stop doing our own rtc management over suspendRussell King2007-07-121-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the RTC management over a suspend/resume cycle. Firstly, we may not be using the internal RTC for time keeping; some platforms have an external RTC for this inspite of the PXA having an internal RTC. Secondly, the RTC library code handles updating system time on resume. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] 4451/1: pxa: make dma.c generic and remove cpu specific dma codeEric Miao2007-07-123-13/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the number of dma channels varies between pxa25x and pxa27x, it introduces some specific code in dma.c. This patch moves the specific code to pxa25x.c and pxa27x.c and makes dma.c more generic. 1. add pxa_init_dma() for dma initialization, the number of channels are passed in by the argument 2. add a "prio" field to the "struct pxa_dma_channel" for the channel priority, and is initialized in pxa_init_dma() 3. use a general priority comparison with the channels "prio" field so to remove the processor specific pxa_for_each_dma_prio macro, this is not lightning fast as the original one, but it is acceptable as it happens when requesting dma, which is usually not so performance critical Signed-off-by: eric miao <eric.miao@marvell.com> Acked-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] 4450/1: pxa: add pxa25x_init_irq() and pxa27x_init_irq()Eric Miao2007-07-1213-23/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | /* should be ok this time, I aligned this patch to your arm:pxa2.mbox */ 1. move pxa25x specific IRQ initialization code to pxa25x_init_irq() and pxa27x code to pxa27x_init_irq(), remove pxa_init_irq() 2. replace all pxa_init_irq() with their PXA25x or PXA27x specific functions Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] 4438/1: PXA: remove #ifdef .. #endif from pxa_gpio_demux_handler()Eric Miao2007-07-121-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. use GPIO_IRQ_mask[] to select those bits of interest, actually only those "unmasked" GPIO IRQs with their corresponding bits in GPIO_IRQ_mask[] set to "1" should be checked 2. remove #ifdef PXA_LAST_GPIO > 96 .. #endif, GPIO_IRQ_mask[] is used to mask out the irrelevant bits, so that even though the GEDR3 on PXA25x is reserved, it will be masked, and the following code will never run. Another point is that GPIO85- GPIO95 bits within GEDR2 will also be masked out on PXA25x Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] 4437/1: PXA: move the GPIO IRQ initialization code to pxa_init_irq_gpio()Eric Miao2007-07-121-24/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | move the GPIO IRQ initialization code to pxa_init_irq_gpio() Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] 4436/1: PXA: move low IRQ initialization code to pxa_init_irq_low()Eric Miao2007-07-121-15/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. move low IRQ initialization code to pxa_init_irq_low() Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] 4435/1: PXA: remove PXA_INTERNAL_IRQSEric Miao2007-07-121-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. define PXA_GPIO_IRQ_BASE to be right after the internal IRQs, and define PXA_GPIO_IRQ_NUM to be 128 for all PXA2xx variants 2. make the code specific to the high IRQ numbers (32..64) to be PXA27x specific 3. add a function pxa_init_irq_high() to initialize the internal high IRQ chip, the invoke of this function could be moved to PXA27x specific initialization code Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] 4434/1: PXA: remove PXA_IRQ_SKIPEric Miao2007-07-121-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. PXA_IRQ_SKIP is defined to be 7 on PXA25x so that the first IRQ starts from zero. This makes IRQ numbering inconsistent between PXA25x and PXA27x. Remove this macro so that the same IRQ_XXXXX definition has the same value on both PXA25x and PXA27x. 2. make IRQ_SSP3..IRQ_PWRI2C valid only if PXA27x is defined, this avoids unintentional use of these macros on PXA25x Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] pxa: Fix PXA27x suspend type validation, remove pxa_pm_prepare()Russell King2007-07-123-27/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pxa_pm_prepare() tried to validate the suspend method type. As noted in previous commits: eb9289eb20df6b54214c45ac7c6bf5179a149026 9c372d06ce9ddf65e1393f9ea22a6d6bd5f96b42 e8c9c502690efd24b7055bf608e7a3c34216848b the checking of the suspend type in the 'prepare' method is the wrong place to do this; use the 'valid' method instead. This means that pxa_pm_prepare() can be entirely removed. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] pxa: move pm_ops structure into CPU specific filesRussell King2007-07-123-29/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the pm_ops structure into the PXA25x and PXA27x support files. Remove the old pxa_pm_prepare() function, and rename the both pxa_cpu_pm_prepare() functions as pxa_pm_prepare(). We'll fix that later. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] pxa: introduce cpu_is_pxaXXX macrosRussell King2007-07-121-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] pxa: use mutexes instead of semaphoresRussell King2007-07-121-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | [ARM] pxa: remove useless pxa_pm_finish() functionRussell King2007-07-122-12/+0
| | | | | | | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pxa_pm_finish() does nothing but return zero. The core code does nothing with this return value, and will not try to call the finish method in the pm_ops structure if it is NULL. Therefore, we can remove this useless function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | * | [ARM] sa1100: remove boot time RTC initialisationRussell King2007-07-121-24/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RTC library code contains everything necessary to set the system time from the RTC; for similar reasons as the previous commit, it's far better to let the RTC library code sort this out rather than implement something which might not be appropriate for everyone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | * | [ARM] sa1100: stop doing our own rtc management over suspendRussell King2007-07-121-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the RTC management over a suspend/resume cycle. As per the corresponding PXA patch, the RTC library code handles updating system time on resume. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | * | [ARM] 4453/1: Fully Decode ARM instruction set state in show_regs() tombstoneGeorge G. Davis2007-07-121-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM show_regs() tombstone only partially decodes which ARM ISA was executing at the time a fault occurred displaying either "(T)" for the Thumb case or nothing at all for other cases. This patch therefore explicitly identifies which state the processor is in at the time of a fault: ARM, Thumb, Jazelle or JazelleEE. Signed-off-by: George G. Davis <gdavis@mvista.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | * | [ARM] 4423/1: add ATAGS supportBill Gatliff2007-07-123-5/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Examines the ATAGS pointer (r2) at boot, and interprets a nonzero value as a reference to an ATAGS structure. A suitable ATAGS structure replaces the kernel's command line. Signed-off-by: Bill Gatliff <bgat@billgatliff.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | * | [ARM] 4393/2: ARMv7: Add uncompressing code for the new CPU Id formatCatalin Marinas2007-07-121-1/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current arch/arm/boot/compressed/head.S code only supports cores to ARMv6 with the old CPU Id format. This patch adds support for the new ARMv6 with the new CPU Id and ARMv7 cores that no longer have the ARMv4 cache operations. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
OpenPOWER on IntegriCloud