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* [CRYPTO] Add x86_64 asm AESAndreas Steinmetz2005-07-064-1/+522
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implementation: =============== The encrypt/decrypt code is based on an x86 implementation I did a while ago which I never published. This unpublished implementation does include an assembler based key schedule and precomputed tables. For simplicity and best acceptance, however, I took Gladman's in-kernel code for table generation and key schedule for the kernel port of my assembler code and modified this code to produce the key schedule as required by my assembler implementation. File locations and Kconfig are kept similar to the i586 AES assembler implementation. It may seem a little bit strange to use 32 bit I/O and registers in the assembler implementation but this gives the best code size. My implementation takes one instruction more per round compared to Gladman's x86 assembler but it doesn't require any stack for local variables or saved registers and it is less serialized than Gladman's code. Note that all comparisons to Gladman's code were done after my code was implemented. I did only use FIPS PUB 197 for the implementation so my implementation is independent work. If anybody has a better assembler solution for x86_64 I'll be pleased to have my code replaced with the better solution. Testing: ======== The implementation passes the in-kernel crypto testing module and I'm running it without any problems on my laptop where it is mainly used for dm-crypt. Microbenchmark: =============== The microbenchmark was done in userspace with similar compile flags as used during kernel compile. Encrypt/decrypt is about 35% faster than the generic C implementation. As the generic C as well as my assembler implementation are both table I don't really expect that there is much room for further improvements though I'll be glad to be corrected here. The key schedule is about 5% slower than the generic C implementation. This is due to the fact that some more work has to be done in the key schedule routine to fit the schedule to the assembler implementation. Code Size: ========== Encrypt and decrypt are together about 2.1 Kbytes smaller than the generic C implementation which is important with regard to L1 cache usage. The key schedule routine is about 100 bytes larger than the generic C implementation. Data Size: ========== There's no difference in data size requirements between the assembler implementation and the generic C implementation. License: ======== Gladmans's code is dual BSD/GPL whereas my assembler code is GPLv2 only (I'm not going to change the license for my code). So I had to change the module license for the x86_64 aes module from 'Dual BSD/GPL' to 'GPL' to reflect the most restrictive license within the module. Signed-off-by: Andreas Steinmetz <ast@domdv.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6Linus Torvalds2005-07-051-2/+3
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| * [SPARC64]: Fix UltraSPARC-III fallout from membar changes.David S. Miller2005-07-051-2/+3
| | | | | | | | | | | | | | | | The membar changes made the size of __cheetah_flush_tlb_pending grow by one instruction, but the boot-time code patching was not updated to match. Signed-off-by: David S. Miller <davem@davemloft.net>
* | [PATCH] kprobes: fix namespace problem and sparc64 buildRusty Lynch2005-07-055-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | The following renames arch_init, a kprobes function for performing any architecture specific initialization, to arch_init_kprobes in order to cleanup the namespace. Also, this patch adds arch_init_kprobes to sparc64 to fix the sparc64 kprobes build from the last return probe patch. Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [PATCH] ppc32: explicitly disable 440GP IRQ compatibility mode in 440GX setupEugene Surovegin2005-07-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add explicit disabling of 440GP IRQ compatibility mode when configuring 440GX interrupt controller. This helps when board firmware for some reason uses this compatibility mode and leaves it enabled. It breaks 440GX interrupt code because it assumes native 440GX IRQ mode. People seems to be continuously bitten by this. Signed-off-by: Eugene Surovegin <ebs@ebshome.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [PATCH] ppc32: stop misusing NTP's time_offset valuejohn stultz2005-07-051-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of my timeofday rework, I've been looking at the NTP code and I noticed that the PPC architecture is apparently misusing the NTP's time_offset (it is a terrible name!) value as some form of timezone offset. This could cause problems when time_offset changed by the NTP code. This patch changes the PPC code so it uses a more clear local variable: timezone_offset. Signed-off-by: John Stultz <johnstul@us.ibm.com> Acked-by: Tom Rini <trini@kernel.crashing.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [PATCH] ppc32: add Freescale MPC885ADS board supportAndrei Konovalov2005-07-056-15/+1515
|/ | | | | | | | | | | | | | | | | | This patch adds the Freescale MPC86xADS board support. The supported devices are SMC UART and 10Mbit ethernet on SCC1. The manual for the board says that it "is compatible with the MPC8xxFADS for software point of view". That's why this patch extends FADS instead of introducing a new platform. FEC is not supported as the "combined FCC/FEC ethernet driver" driver by Pantelis Antoniou should replace the current FEC driver. Signed-off-by: Gennadiy Kurtsman <gkurtsman@ru.mvista.com> Signed-off-by: Andrei Konovalov <akonovalov@ru.mvista.com> Acked-by: Tom Rini <trini@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Merge rsync://rsync.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6Linus Torvalds2005-07-057-443/+306
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| * [SPARC64]: Fix IRQ retry interval timer value on sparc64 PCI controllers.David S. Miller2005-07-042-5/+2
| | | | | | | | | | | | Use '5' instead of 'infinity'. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Small Schizo PCI controller programming tweaks.David S. Miller2005-07-041-15/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Use macro instead of magic value for Tomatillo discard- timeout interrupt enable register bit. Leave OBP programming PTO value unless Tomatillo and version >= 0x2. If no-bus-parking property is present, explicitly clear PCICTRL_PARK bit. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Do proper DMA IRQ syncing on TomatilloDavid S. Miller2005-07-041-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was the main impetus behind adding the PCI IRQ shim. In order to properly order DMA writes wrt. interrupts, you have to write to a PCI controller register, then poll for that bit clearing. There is one bit for each interrupt source, and setting this register bit tells Tomatillo to drain all pending DMA from that device. Furthermore, Tomatillo's with revision less than 4 require us to do a block store due to some memory transaction ordering issues it has on JBUS. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Add support for IRQ pre-handlers.David S. Miller2005-07-044-423/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows a PCI controller to shim into IRQ delivery so that DMA queues can be drained, if necessary. If some bus specific code needs to run before an IRQ handler is invoked, the bus driver simply needs to setup the function pointer in bucket->irq_info->pre_handler and the two args bucket->irq_info->pre_handler_arg[12]. The Schizo PCI driver is converted over to use a pre-handler for the DMA write-sync processing it needs when a device is behind a PCI->PCI bus deeper than the top-level APB bridges. While we're here, clean up all of the action allocation and handling. Now, we allocate the irqaction as part of the bucket->irq_info area. There is an array of 4 irqaction (for PCI irq sharing) and a bitmask saying which entries are active. The bucket->irq_info is allocated at build_irq() time, not at request_irq() time. This simplifies request_irq() and free_irq() tremendously. The SMP dynamic IRQ retargetting code got removed in this change too. It was disabled for a few months now, and we can resurrect it in the future if we want. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64/COMPAT]: Add some compat ioctl for ppdevRaphael Assenat2005-07-041-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following patch adds some ioctls to include/linux/compat_ioctl.h to allow using ppdev from the 32 bit user space on sparc64. This patch also adds the PPDEV option in the sparc64 menu, near Parallel printer support in the 'General machine setup' submenu. All those ioctls seem to be compatible, since (correct me if I'm wrong) they dont use the 'long' type. See include/linux/ppdev.h. The application I used to test the new ioctls only used the following: PPEXCL PPCLAIM PPNEGOT PPGETMODES PPRCONTROL PPWCONTROL PPDATADIR PPWDATA PPRDATA But I beleive that the other ioctls will work fine. Signed-off-by: David S. Miller <davem@davemloft.net>
* | Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6Linus Torvalds2005-07-053-4/+10
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| * | [PATCH] PCI: clean up dynamic pci id logicGreg Kroah-Hartman2005-07-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dynamic pci id logic has been bothering me for a while, and now that I started to look into how to move some of this to the driver core, I thought it was time to clean it all up. It ends up making the code smaller, and easier to follow, and fixes a few bugs at the same time (dynamic ids were not being matched everywhere, and so could be missed on some call paths for new devices, semaphore not needed to be grabbed when adding a new id and calling the driver core, etc.) I also renamed the function pci_match_device() to pci_match_id() as that's what it really does. Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * | [PATCH] PCI: pci_assign_unassigned_resources() on x86Ivan Kokshaysky2005-07-012-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add sanity check for io[port,mem]_resource in setup-bus.c. These resources look like "free" as they have no parents, but obviously we must not touch them. - In i386.c:pci_allocate_bus_resources(), if a bridge resource cannot be allocated for some reason, then clear its flags. This prevents any child allocations in this range, so the setup-bus code will work with a clean resource sub-tree. - i386.c:pcibios_enable_resources() doesn't enable bridges, as it checks only resources 0-5, which looks like a clear bug to me. I suspect it might break hotplug as well in some cases. From: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | | [PATCH] ARM: Fix non-standard PXA io_pg_offst initialisersRussell King2005-07-045-7/+7
| | | | | | | | | | | | | | | | | | These didn't match my sed expression correctly, fix them up manually. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [PATCH] ARM: Change 'param_offset' to 'boot_params'Russell King2005-07-041-2/+2
| |/ |/| | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [PATCH] ARM: 2784/1: Fix the block cache flush operation rangeCatalin Marinas2005-07-031-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Catalin Marinas The range for the ARMv6 block cache operations is inclusive but the kernel doesn't re-calculate the end address, causing a page fault when used (this only happens with support for cache aliasing, otherwise the blk_flush_kern_dcache_page() is not called). This patch subtracts L1_CACHE_BYTES from the end address. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [PATCH] ARM: Remove machine description macrosRussell King2005-07-0371-453/+607
| | | | | | | | | | | | | | Remove the pointless machine description macros, favouring C99 initialisers instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2005-07-026-818/+53
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| * | [PATCH] ARM: replace schedule_timeout() with msleep()Nishanth Aravamudan2005-07-011-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use msleep() instead of schedule_timeout() to guarantee the task delays as expected. Neither signals nor wait-queue events are important at this point in the code, I believe. Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com> Signed-off-by: Domen Puncer <domen@coderock.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [PATCH] ARM: Make the magic values in head.S more obviousRussell King2005-07-011-12/+8
| | | | | | | | | | | | | | | | | | | | | Make the magic address values in head.S more obvious as to where they came from. Wrap all debug code in CONFIG_DEBUG_LL. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [PATCH] ARM: 2783/1: Remove omnimeter_defconfig as there is no kernel supportBen Dooks2005-07-011-803/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Ben Dooks The omnimeter_defconfig does not define any machines and seems to have no other support in the current kernel. This patch removes the config file, as this is the only thing currently mentioning the ominmeter. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [PATCH] ARM: 2781/2: PXA27x Standby mode take 2Todd Poynor2005-07-013-1/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Todd Poynor Add support for PXA27x Standby mode, a low-power mode that retains CPU and some peripheral state (the existing "sleep" mode is a power-power mode that retains less state). Activated via: echo -n standby > /sys/power/state From: David Burrage and Todd Poynor Signed-off-by: Todd Poynor <tpoynor@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [PATCH] alpha smp fix (part #2)Ivan Kokshaysky2005-07-011-0/+2
| |/ |/| | | | | | | | | | | | | | | | | | | This fixes the bug that caused BUG_ON(!irqs_disabled()) to trigger in run_posix_cpu_timers() on alpha/smp. We didn't disable interrupts properly before calling smp_percpu_timer_interrupt(). We *do* disable interrupts everywhere except this unfortunate smp_percpu_timer_interrupt(). Fixed thus. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [PATCH] alpha smp fixIvan Kokshaysky2005-06-301-1/+1
|/ | | | | | | | | | | | As usual, the reason of this breakage is quite silly: in do_entIF, we are checking for PS == 0 to see whether it was a kernel BUG() or userspace trap. It works, unless BUG() happens in interrupt - PS is not 0 in kernel mode due to non-zero IPL, and the things get messed up horribly then. In this particular case it was BUG_ON(!irqs_disabled()) triggered in run_posix_cpu_timers(), so we ended up shooting "current" with the bursts of one SIGTRAP and three SIGILLs on every timer tick. ;-)
* Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2005-06-305-50/+47
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| * [PATCH] ARM: 2779/1: Fix the V bit setting for the ARM1020x CPUsCatalin Marinas2005-06-302-4/+4
| | | | | | | | | | | | | | | | | | | | | | Patch from Catalin Marinas This patch fixes the V bit setting for the ARM1020x processors. At reset, this bit is automatically set to the value of the HIVECSINIT input signal which just happened to be 1 but it is not mandatory. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [PATCH] ARM: 2778/1: Add -mno-thumb-interwork to CFLAGS_ABICatalin Marinas2005-06-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Catalin Marinas The new EABI gcc adds -mthumb-interwork by default, even if -mabi=apcs-gnu is passed. This causes a warning for every compiled C file when -march=armv4 is used. The patch adds -mno-thumb-interwork if the option is supported. This is also useful since we don't need any ARM/Thumb interworking in the kernel Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [PATCH] ARM: 2777/1: Fix broken comment arch/arm/mm/proc-arm1020.SCatalin Marinas2005-06-301-1/+1
| | | | | | | | | | | | | | | | | | | | Patch from Catalin Marinas This patch fixes a broken comment in the proc-arm1020.S file which prevents the file compilation Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [PATCH] ARM: Don't try to send a signal to pid0Russell King2005-06-302-45/+42
| | | | | | | | | | | | | | | | | | If we receive an unrecognised abort during boot, don't try to send a signal to pid0, but instead report the current state. This leads to less confusing debug reports. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge rsync://rsync.kernel.org/pub/scm/linux/kernel/git/paulus/ppc64-2.6Linus Torvalds2005-06-3016-518/+285
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| * | [PATCH] ppc64: Replace custom locking code with a spinlockMichael Ellerman2005-06-301-36/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hvlpevent_queue (formally ItLpQueue) has a member called xInUseWord which is used for serialising access to the queue. Because it's a word (ie. 32 bit) there's a custom 32-bit version of test_and_set_bit() or thereabouts in ItLpQueue.c. The xInUseWord is not shared with they hypervisor, so we can replace it with a spinlock and remove the custom code. There is also another locking mechanism (ItLpQueueInProcess). This is redundant because it's only manipulated while the lock's held. Remove it. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Formatting cleanups in arch/ppc64/kernel/ItLpQueue.cMichael Ellerman2005-06-301-31/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just formatting cleanups: * rename some "nextLpEvent" variables to just "event" * make code fit in 80 columns * use brackets around if/else * use a temporary to make hvlpevent_clear_valid clearer Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Cleanup whitespace in arch/ppc64/kernel/ItLpQueue.cMichael Ellerman2005-06-301-29/+29
| | | | | | | | | | | | | | | | | | | | | | | | Just cleanup white space. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Cleanup proc printing of event typesMichael Ellerman2005-06-301-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code that prints event counts by type uses a hand-coded number of tabs to get the alignment right. Instead use a printf alignment which will allow allow us to use the event_type strings elsewhere in the future. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Simplify counting of lpevents, remove lpevent_count from pacaMichael Ellerman2005-06-301-15/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently there's a per-cpu count of lpevents processed, a per-queue (ie. global) total count, and a count by event type. Replace all that with a count by event for each cpu. We only need to add it up int the proc code. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Don't count number of events processed for callerMichael Ellerman2005-06-304-13/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we count the number of lpevents processed in 3 seperate places. One of these counters is never read, so just remove it. This means hvlpevent_queue_process() no longer needs to return the number of events processed. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Rename ItLpQueue_* functions to hvlpevent_queue_*Michael Ellerman2005-06-305-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we've renamed the xItLpQueue structure, rename the functions that operate on it also. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Rename xItLpQueue to hvlpevent_queueMichael Ellerman2005-06-302-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | The xItLpQueue is a queue of HvLpEvents that we're given by the Hypervisor. Rename xItLpQueue to hvlpevent_queue and make the type struct hvlpevent_queue. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Move definition of xItLpQueueMichael Ellerman2005-06-302-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | The xItLpQueue is declared in LparData.c, move it into ItLpQueue.c. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Make two ItLpQueue related functions staticMichael Ellerman2005-06-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | External parties don't need to use ItLpQueue_getNextLpEvent() or ItLpQueue_clearValid(), they're internal to ItLpQueue.c Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Move xItLpQueue proc code into ItLpQueue.cMichael Ellerman2005-06-302-48/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the code that displays xItLpQueue values in /proc into ItLpQueue.c. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Move initialisation of xItLpQueue into ItLpQueue.cMichael Ellerman2005-06-302-20/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | The xItLpQueue is initalised manually in iSeries_setup_arch(). Move this code into ItLpQueue.c for a cleaner separation. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Don't pass the pointers to xItLpQueue aroundMichael Ellerman2005-06-305-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | Because there's only one ItLpQueue and we know where it is, ie. xItLpQueue, there's no point passing pointers to it it around all over the place. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Reorganise the paca initialisation macrosMichael Ellerman2005-06-301-146/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the macros that initialise the paca to remove the lpq parameter. It also rearranges them a bit with the hope of making them a bit clearer. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Move set_spread_lpevents() into ItLpQueue.cMichael Ellerman2005-06-302-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only code outside ItLpQueue.c that refers to spread_lpevents is in set_apread_lpevents(), so move it inside ItLpQueue.c and make spread_lpevents static. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Spread lpevents by default on iSeriesMichael Ellerman2005-06-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | With the previous patch in place, spreading lpevents by default becomes a one liner. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * | [PATCH] ppc64: Remove lpqueue pointer from the paca on iSeriesMichael Ellerman2005-06-307-26/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The iSeries code keeps a pointer to the ItLpQueue in its paca struct. But all these pointers end up pointing to the one place, ie. xItLpQueue. So remove the pointer from the paca struct and just refer to xItLpQueue directly where needed. The only complication is that the spread_lpevents logic was implemented by having a NULL lpqueue pointer in the paca on CPUs that weren't supposed to process events. Instead we just compare the spread_lpevents value to the processor id to get the same behaviour. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
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