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* x86: Cleanup the genirq name spaceThomas Gleixner2011-03-128-48/+51
| | | | | | | genirq is switching to a consistent name space for the irq related functions. Convert x86. Conversion was done with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* Merge branch 'x86/apic' into x86/irqThomas Gleixner2011-03-1235-586/+702
|\ | | | | | | | | | | | | Reason: Update to latest genirq code conflicts with pending apic changes Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * x86: ioapic: Move trigger defines to io_apic.hThomas Gleixner2011-02-232-4/+4
| | | | | | | | | | | | Required for devicetree based io_apic configuration. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * x86: ioapic: Implement and use io_apic_setup_irq_pin_once()Thomas Gleixner2011-02-231-32/+25
| | | | | | | | | | | | | | | | | | | | io_apic_set_pci_routing() and mp_save_irq() check the pin_programmed bit before calling io_apic_setup_irq_pin() and set the bit when the pin was setup. Move that duplicated code into a separate function and use it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * x86: ioapic: Remove useless inlinesThomas Gleixner2011-02-231-12/+2
| | | | | | | | | | | | | | | | There is no point to have irq_trigger() and irq_polarity() as wrappers around the MPBIOS_* camel case functions. Get rid of both the inlines and the ugly camel case. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * x86: ioapic: Make a few functions staticThomas Gleixner2011-02-232-32/+28
| | | | | | | | | | | | No users outside of io_apic.c. Mark bad_ioapic() __init while at it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * x86: ioapic: Use setup function in setup_IO_APIC_irq_extra()Thomas Gleixner2011-02-231-10/+6
| | | | | | | | | | | | | | Another version of the same thing. Only set the pin programmed, when the setup function succeeds. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * x86: ioapic: Use setup function in __io_apic_setup_irqs()Thomas Gleixner2011-02-231-12/+5
| | | | | | | | | | | | Replace the duplicated code. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * x86: ioapic: Use setup function in __io_apic_set_pci_routing()Thomas Gleixner2011-02-231-31/+3
| | | | | | | | | | | | | | | | The only difference here is that we did not call __add_pin_to_irq_node() for the legacy irqs, but that's not worth 30 lines of extra code. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * x86: ioapic: Use new setup function in pre_init_apic_IRQ0()Thomas Gleixner2011-02-231-7/+2
| | | | | | | | | | | | | | | | Remove the duplicated code and call the function. It does not matter whether we allocated the cfg before calling setup_local_APIC() and we can set the irq chip and handler after that as well. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * x86: ioapic: Add io_apic_setup_irq_pin()Thomas Gleixner2011-02-232-0/+17
| | | | | | | | | | | | | | | | There are about four places in the ioapic code which do exactly the same setup sequence. Also the OF based ioapic setup needs that function to avoid putting the OF specific code into ioapic.c Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * x86: ioapic: Split out the nested loop in setup_IO_APIC_irqs()Thomas Gleixner2011-02-231-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Two consecutive for(...) for(...) lines to avoid an extra indentation are just horrible to read. I had to look more than once to figure out what the code is doing. Split out the inner loop into a separate function. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * x86: ioapic: Remove silly debug bloat in setup_IOAPIC_irqs()Thomas Gleixner2011-02-231-20/+12
| | | | | | | | | | | | | | This is debug code and it does not matter at all whether we print each not connected pin in an extra line or try to be extra clever. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * x86: Fix deps of X86_UP_IOAPICHenrik Kretzschmar2011-02-231-1/+1
| | | | | | | | | | | | | | | | | | Since commit 7cd92366a593246650cc7d6198e2c7d3af8c1d8a lAPIC enabled accidently the IOAPIC, which now gets fixed. Signed-off-by: Henrik Kretzschmar <henne@nachtwindheim.de> LKML-Reference: <1298385487-4708-5-git-send-email-henne@nachtwindheim.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86: Add dummy functions for compiling without IOAPICHenrik Kretzschmar2011-02-232-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds IOAPIC dummy functions for compilation with local APIC, but without IOAPIC. The local variable ioapic_entries in enable_IR_x2apic() does not need initialization anymore, since the dummy returns NULL. Signed-off-by: Henrik Kretzschmar <henne@nachtwindheim.de> LKML-Reference: <1298385487-4708-4-git-send-email-henne@nachtwindheim.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86: Rework arch_disable_smp_support() for x86Henrik Kretzschmar2011-02-234-4/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently arch_disable_smp_support() on x86 disables only the support for the IOAPIC and is also compiled in if SMP-support is not. Therefore this function is renamed to disable_ioapic_support(), which meets its purpose and is only compiled in the kernel when IOAPIC support is also. A new arch_disable_smp_support() is created in smpboot.c, which calls disable_ioapic_support() and gets only compiled in the kernel when SMP support is also. Signed-off-by: Henrik Kretzschmar <henne@nachtwindheim.de> LKML-Reference: <1298385487-4708-3-git-send-email-henne@nachtwindheim.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86: Add dummy mp_save_irq()Henrik Kretzschmar2011-02-231-0/+1
| | | | | | | | | | | | | | | | This is a dummy function, used when no IOAPIC is compiled in. Signed-off-by: Henrik Kretzschmar <henne@nachtwindheim.de> LKML-Reference: <1298385487-4708-2-git-send-email-henne@nachtwindheim.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86: Move ioapic_irq_destination_types to apicdef.hHenrik Kretzschmar2011-02-232-11/+12
| | | | | | | | | | | | | | | | | | This enum is used by non IOAPIC code, so apicdef.h is the best place for it. Signed-off-by: Henrik Kretzschmar <henne@nachtwindheim.de> LKML-Reference: <1298385487-4708-1-git-send-email-henne@nachtwindheim.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * Merge branch 's5p-fixes-for-linus' of ↵Linus Torvalds2011-02-219-363/+342
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung * 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: S5PV210: Fix regulator names ARM: S5PV210: Update max8998_platform_data ARM: SAMSUNG: Drop exporting s3c24xx_ts_set_platdata ARM: S5P: Fix end address in memory resource information for UART devices ARM: S5P64X0: Cleanup map.h file ARM: S5P6442: Cleanup map.h file ARM: S5PC100: Clenaup map.h file ARM: S5PV210: Cleanup map.h file ARM: S5PV310: Cleanup map.h file
| | * ARM: S5PV210: Fix regulator namesMarek Szyprowski2011-02-182-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 1130e5b3ff4 regulators are exported to debugfs. The names of the regulators that contains slash ('/') causes an ops during kernel boot. This patch fixes this issue. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * ARM: S5PV210: Update max8998_platform_dataMarek Szyprowski2011-02-182-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Max8998 PMIC driver's platform data has been changed once again in commit 735a3d9efdc. This patch fixes build break caused by that commit. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * ARM: SAMSUNG: Drop exporting s3c24xx_ts_set_platdataAxel Lin2011-02-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | s3c24xx_ts_set_platdata is annotated __init and not used by any module, thus don't export it. This patch fixes below warning: WARNING: arch/arm/plat-samsung/built-in.o(__ksymtab+0x90): Section mismatch in reference from the variable __ksymtab_s3c24xx_ts_set_platdata to the function .init.text:s3c24xx_ts_set_platdata() The symbol s3c24xx_ts_set_platdata is exported and annotated __init Fix this by removing the __init annotation of s3c24xx_ts_set_platdata or drop the export. Signed-off-by: Axel Lin <axel.lin@gmail.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * ARM: S5P: Fix end address in memory resource information for UART devicesThomas Abraham2011-02-171-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | For S5P platforms, the end address in memory resource information for UART devices is one byte more than the intended value. Fix this by reducing the end address by one byte. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * ARM: S5P64X0: Cleanup map.h fileKukjin Kim2011-02-171-41/+42
| | | | | | | | | | | | Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * ARM: S5P6442: Cleanup map.h fileKukjin Kim2011-02-171-32/+37
| | | | | | | | | | | | Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * ARM: S5PC100: Clenaup map.h fileKukjin Kim2011-02-171-110/+83
| | | | | | | | | | | | Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * ARM: S5PV210: Cleanup map.h fileKukjin Kim2011-02-171-85/+83
| | | | | | | | | | | | Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * ARM: S5PV310: Cleanup map.h fileKukjin Kim2011-02-171-76/+73
| | | | | | | | | | | | Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2011-02-2117-37/+175
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6745/1: kprobes insn decoding fix ARM: tlb: move noMMU tlb_flush() to asm/tlb.h ARM: tlb: delay page freeing for SMP and ARMv7 CPUs ARM: Keep exit text/data around for SMP_ON_UP ARM: Ensure predictable endian state on signal handler entry ARM: 6740/1: Place correctly notes section in the linker script ARM: 6700/1: SPEAr: Correct SOC config base address for spear320 ARM: 6722/1: SPEAr: sp810: switch to slow mode before reset ARM: 6712/1: SPEAr: replace readl(), writel() with relaxed versions in uncompress.h ARM: 6720/1: SPEAr: Append UL to VMALLOC_END ARM: 6676/1: Correct the cpu_architecture() function for ARMv7 ARM: 6739/1: update .gitignore for boot/compressed ARM: 6743/1: errata: interrupted ICALLUIS may prevent completion of broadcasted operation ARM: 6742/1: pmu: avoid setting IRQ affinity on UP systems ARM: 6741/1: errata: pl310 cache sync operation may be faulty
| | * | ARM: 6745/1: kprobes insn decoding fixNicolas Pitre2011-02-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Marcin Slusarz says: > In arch/arm/kernel/kprobes-decode.c there's a function > arm_kprobe_decode_insn which does: > > } else if ((insn & 0x0e000000) == 0x0c400000) { > ... > > This is always false, so code below is dead. > I found this bug by coccinelle (http://coccinelle.lip6.fr/). Reported-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: tlb: move noMMU tlb_flush() to asm/tlb.hRussell King2011-02-212-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no need to noMMU to put tlb_flush() in asm/tlbflush.h - it's part of the tlb shootdown interface. Move it to asm/tlb.h instead, as per x86. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: tlb: delay page freeing for SMP and ARMv7 CPUsRussell King2011-02-211-13/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to delay freeing any mapped page on SMP and ARMv7 systems to ensure that the data is not accessed by other CPUs, or is used for speculative prefetch with ARMv7. This includes not only mapped pages but also pages used for the page tables themselves. This avoids races with the MMU/other CPUs accessing pages after they've been freed but before we've invalidated the TLB. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: Keep exit text/data around for SMP_ON_UPRussell King2011-02-211-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When SMP_ON_UP is used and the spinlocks are inlined, we end up with inline spinlocks in the exit code, with references from the SMP alternatives section to the exit sections. This causes link time errors. Avoid this by placing the exit sections in the init-discarded region. Cc: <stable@kernel.org> Tested-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: Ensure predictable endian state on signal handler entryRussell King2011-02-211-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure a predictable endian state when entering signal handlers. This avoids programs which use SETEND to momentarily switch their endian state from having their signal handlers entered with an unpredictable endian state. Cc: <stable@kernel.org> Acked-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6740/1: Place correctly notes section in the linker scriptPawel Moll2011-02-212-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 18991197b4b588255ccabf472ebc84db7b66a19c added --build-id linker option when toolchain supports it. ARM one does, but for some reason places the section at 0 when linker script doesn't mention it explicitly. The 1e621a8e3752367d4aae78a8ab00a18fb2793f34 worked around the problem removing this section from binary image with explicit objcopy options, but it still exists in vmlinux, confusing tools like debuggers and perf. This problem was discussed here: http://lists.infradead.org/pipermail/linux-arm-kernel/2010-May/015994.html http://lists.infradead.org/pipermail/linux-arm-kernel/2010-May/015994.html but the proposed changes to the linker script were substantial. This patch simply places NOTES (36 bytes long, at least when compiled with CodeSourcery toolchain) between data and bss, which seem to be the right place (and suggested by the sample linker script in include/asm-generic/vmlinux.lds.h). It is enough to place it correctly in vmlinux (so debuggers are happy): Section Headers: [11] .data PROGBITS c07ce000 7ce000 020fc0 00 WA 0 0 32 [12] .notes NOTE c07eefc0 7eefc0 000024 00 AX 0 0 4 [13] .bss NOBITS c07ef000 7eefe4 01e628 00 WA 0 0 32 Program Headers: LOAD 0x008000 0xc0008000 0xc0008000 0x7e6fe4 0x805628 RWE 0x8000 NOTE 0x7eefc0 0xc07eefc0 0xc07eefc0 0x00024 0x00024 R E 0x4 Section to Segment mapping: Segment Sections... 00 <...> .data .notes .bss 01 .notes and to get it exposed as /sys/kernel/notes used by perf tools. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6700/1: SPEAr: Correct SOC config base address for spear320viresh kumar2011-02-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPEAR320_SOC_CONFIG_BASE was wrong, causing the wrong registers to be accessed. Reviewed-by: Stanley Miao <stanley.miao@windriver.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6722/1: SPEAr: sp810: switch to slow mode before resetShiraz Hashim2011-02-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In sysctl_soft_reset(), switch to slow mode before resetting the system via the system controller. This is required. Reviewed-by: Stanley Miao <stanley.miao@windriver.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6712/1: SPEAr: replace readl(), writel() with relaxed versions in ↵viresh kumar2011-02-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | uncompress.h readl() and writel() calls the outer cache maintainance operations which are not available during Linux uncompression. This patch replaces readl() and writel() with readl_relaxed() and writel_relaxed() to avoid the link time errors. Reviewed-by: Stanley Miao <stanley.miao@windriver.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6720/1: SPEAr: Append UL to VMALLOC_ENDviresh kumar2011-02-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes following warning: arch/arm/mm/init.c:606: warning: format '%08lx' expects type 'long unsigned int', but argument 12 has type 'unsigned int' by appending UL to VMALLOC_END's Number. Reviewed-by: Stanley Miao <stanley.miao@windriver.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6676/1: Correct the cpu_architecture() function for ARMv7Catalin Marinas2011-02-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If ID_MMFR0[3:0] >= 3, the architecture version is ARMv7. The code was currently only testing for ID_MMFR0[3:0] == 3. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6739/1: update .gitignore for boot/compressedNicolas Pitre2011-02-191-1/+5
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6743/1: errata: interrupted ICALLUIS may prevent completion of ↵Will Deacon2011-02-192-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | broadcasted operation On versions of the Cortex-A9 prior to r3p0, an interrupted ICIALLUIS operation may prevent the completion of a following broadcasted operation if the second operation is received by a CPU before the ICIALLUIS has completed, potentially leading to corrupted entries in the cache or TLB. This workaround sets a bit in the diagnostic register of the Cortex-A9, causing CP15 maintenance operations to be uninterruptible. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6742/1: pmu: avoid setting IRQ affinity on UP systemsWill Deacon2011-02-191-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we can execute a CONFIG_SMP kernel on a uniprocessor system, extra care has to be taken in the PMU IRQ affinity setting code to ensure that we don't always fail to initialise. This patch changes the CPU PMU initialisation code so that when we only have a single IRQ, whose affinity can not be changed at the controller, we report success (0) rather than -EINVAL. Reported-by: Avik Sil <avik.sil@linaro.org> Acked-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6741/1: errata: pl310 cache sync operation may be faultySrinidhi Kasagar2011-02-193-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The effect of cache sync operation is to drain the store buffer and wait for all internal buffers to be empty. In normal conditions, store buffer is able to merge the normal memory writes within its 32-byte data buffers. Due to this erratum present in r3p0, the effect of cache sync operation on the store buffer still remains when the operation completes. This means that the store buffer is always asked to drain and this prevents it from merging any further writes. This can severely affect performance on the write traffic esp. on Normal memory NC one. The proposed workaround is to replace the normal offset of cache sync operation(0x730) by another offset targeting an unmapped PL310 register 0x740. Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | Merge branch 'for-linus' of git://git390.marist.edu/pub/scm/linux-2.6Linus Torvalds2011-02-213-10/+22
| |\ \ \ | | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of git://git390.marist.edu/pub/scm/linux-2.6: [S390] net: provide architecture specific NET_SKB_PAD [S390] atomic: use inline asm [S390] correct ipl parameter block safe guard [S390] atomic: use ACCESS_ONCE() for atomic_read() [S390] dasd: correct device table
| | * | [S390] net: provide architecture specific NET_SKB_PADHorst Hartmann2011-02-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NET_SKB_PAD has been increased from 32 to 64 and later to max(32, L1_CACHE_BYTES). This led to a 25% throughput decrease for streaming workloads accompanied by a 37% CPU cost increase on s390. Define a architecture specific NET_SKB_PAD with the old value of 32. Signed-off-by: Horst Hartmann <horsth@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
| | * | [S390] atomic: use inline asmHeiko Carstens2011-02-171-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use inline assemblies for atomic_read/set(). This way there shouldn't be any questions or subtle volatile semantics left. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
| | * | [S390] correct ipl parameter block safe guardMartin Schwidefsky2011-02-171-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'output' variable is passed from decompress_kernel to check_ipl_parmblock before it is initialized. That disables the safe guard against the overwrite of the ipl parameter block. Fix this by passing the correct value to check_ipl_parmblock. Reported-by: David Binderman <dcb314@hotmail.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
| | * | [S390] atomic: use ACCESS_ONCE() for atomic_read()Heiko Carstens2011-02-171-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's make atomic_read() and atomic_set() behave like on all/most other architectures. Generated code is identical with gcc 4.5.2. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* | | | x86: Eliminate pointless adjustment attempts in fixup_irqs()Jan Beulich2011-02-181-1/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not only when an IRQ's affinity equals cpu_online_mask is there no need to actually try to adjust the affinity, but also when it's a subset thereof. This particularly avoids adjustment attempts during system shutdown to any IRQs bound to CPU#0. Signed-off-by: Jan Beulich <jbeulich@novell.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Eric W. Biederman <ebiederm@xmission.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Cc: Gary Hade <garyhade@us.ibm.com> LKML-Reference: <4D5D52C2020000780003272C@vpn.id2.novell.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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