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* [ARM] pxa/zeus: Allow usage of 8250-compatible UART in uncompressMarc Zyngier2010-03-021-0/+6
| | | | | | | | | Zeus console port is wired to a 8250-compatible device (pxa UARTs are reserved to other uses). This patch allows such a configuration in the uncompress sequence. Signed-off-by: Marc Zyngier <maz@misterjones.org> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: refactor uncompress.h for non-PXA uartsEric Miao2010-03-021-7/+28
| | | | | | | | | | | | | | The original patch came from Marc Zyngier where support of 8250-compatible UART is required to show the uncompress information. Modified a little bit here, including changes below: 1. #include <mach/regs-uart.h> is actually not necessary 2. introduced uart_{read,write}() for different base and shift 3. introduced uart_is_enabled() and assumed enabled always for non-PXA uarts Signed-off-by: Eric Miao <eric.y.miao@gmail.com> Acked-by: Marc Zyngier <maz@misterjones.org>
* [ARM] mmp2: fix incorrect calling of chip->mask_ack() for 2nd level cascaded ↵Eric Miao2010-03-021-1/+5
| | | | | | | | | | IRQs The irq_chip is not yet registered, so no default irq_chip.mask_ack(), which we have to handle it correctly manually here. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] mmp2: add handling on PMIC IRQHaojian Zhuang2010-03-023-1/+22
| | | | | | | | | Since PMIC INT pin is a special pin of CPU, the status of PMIC INT pin needs to be cleared after PMIC IRQ occured. Now append the clear operation in irq chip handler. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] mmp2: add support for board IRQsHaojian Zhuang2010-03-021-1/+5
| | | | | Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] mmp2: add missing ICU register definitionsHaojian Zhuang2010-03-021-0/+12
| | | | | Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] mmp2: add gpio initializationHaojian Zhuang2010-03-023-1/+25
| | | | | Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] mmp2: add mfpr settingHaojian Zhuang2010-03-022-0/+11
| | | | | Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] mmp2: add mask function in irq-mmp2.cHaojian Zhuang2010-03-021-0/+2
| | | | | Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] mmp: support jasper development boardHaojian Zhuang2010-03-023-0/+91
| | | | | Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] mmp: add default configuration for MMP2Haojian Zhuang2010-03-021-0/+1194
| | | | | Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] mmp: add support for Marvell MMP2Haojian Zhuang2010-03-0216-8/+892
| | | | | | | | | Marvell MMP2 (aka ARMADA610) is a SoC based on PJ4 core. It's ARMv6 compatible. Support basic interrupt handler and timer, and basic support for MMP2 based FLINT platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] mmp: rename irq.c to irq-pxa168.c to allow other SoC IRQ chipsEric Miao2010-03-022-3/+3
| | | | Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] mmp: update pxa168_defconfig and include avengers lite supportHaojian Zhuang2010-03-021-73/+156
| | | | | | | | Signed-off-by: Gavin Gu <gavin.gu@marvell.com> Signed-off-by: Jing Xiang <jxiang@marvell.com> Signed-off-by: Jack Ren <jack.ren@marvell.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] mmp: avengers lite (pxa168) board bring upHaojian Zhuang2010-03-025-4/+72
| | | | | | | | Signed-off-by: Gavin Gu <gavin.gu@marvell.com> Signed-off-by: Jing Xiang <jxiang@marvell.com> Signed-off-by: Jack Ren <jack.ren@marvell.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa/imote2: Remove redundant pin entry for nCS.Stefan Schmidt2010-03-021-2/+1
| | | | | | | Also remove a trailing whitespace while being there. Signed-off-by: Stefan Schmidt <stefan@datenfreihafen.org> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa/imote2: Add defconfig for the imote2 platform.Stefan Schmidt2010-03-021-0/+2077
| | | | | Signed-off-by: Stefan Schmidt <stefan@datenfreihafen.org> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: introduce PXA_SSP_LEGACY for legacy SSP APIEric Miao2010-03-023-0/+13
| | | | Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: define zeus_power_off() only when CONFIG_PM enabledStefan Schmidt2010-03-021-0/+4
| | | | | | | | | | | | Add some safety check for CONFIG_PM around zeus_power_off(). Without it linking can fail like this: arch/arm/mach-pxa/built-in.o: In function `zeus_power_off': e800.c:(.text+0x2bc8): undefined reference to `pxa27x_cpu_suspend' Signed-off-by: Stefan Schmidt <stefan@datenfreihafen.org> Acked-by: Marc Zyngier <maz@misterjones.org> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: enable check_scoop_reg() only if CONFIG_PM is set.Stefan Schmidt2010-03-021-1/+1
| | | | | | | | | | | This function gets only called from scoop_suspend() and scoop_resume() which are only built in if we have CONFIG_PM set. Make it the same for check_scoop_reg(). This fixes the following warning: arch/arm/common/scoop.c:143: warning: ‘check_scoop_reg’ defined but not used Signed-off-by: Stefan Schmidt <stefan@datenfreihafen.org> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: add support for Embedian MXM-8x10Edwin Peer2010-03-026-0/+867
| | | | | Signed-off-by: Edwin Peer <epeer@tmtservices.co.za> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: move board board IRQ definitions out of irqs.hEric Miao2010-03-027-66/+62
| | | | Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] sa1111: allow cascaded IRQs to be used by platformsEric Miao2010-03-028-130/+116
| | | | Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] locomo: allow cascaded IRQ base to be specified by platformsEric Miao2010-03-026-39/+48
| | | | Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] locomo: remove unused IRQs and avoid unnecessary cascadeEric Miao2010-03-024-314/+11
| | | | | | | | | | | | | IRQ_LOCOMO_* are never used elsewhere, remove these definitions. As well as the cascade of these IRQs. IRQ_LOCOMO_*_BASE changed to IRQ_LOCOMO_*. IRQ_LOCOMO_LT and IRQ_LOCOMO_SPI are likely to be used in a same way as IRQ_LOCOMO_KEY. IRQ_LOCOMO_GPIO and the demultiplex handler should really be living somewhere else. Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] locomo: avoid unnecessary cascaded keyboard IRQEric Miao2010-03-023-61/+8
| | | | | | | | It is not necessary and is over-complicated for IRQ_LOCOMO_KEY to be a cascaded IRQ of IRQ_LOCOMO_KEY_BASE. Removed and introduced locomokbd_{open,close} for masking/unmasking of the keyboard IRQ. Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] sa1100: remove unreferenced IRQ definitionsEric Miao2010-03-021-7/+0
| | | | | | | These IRQ definitions related to LOCOMO are never referenced anywhere, thus could be safely removed. Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa/tosa: make use of the matrix keypad driverEric Miao2010-03-021-19/+98
| | | | | Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa/cm-x270: avoid direct access of GPIO/MFP registersEric Miao2010-03-021-19/+43
| | | | | Cc: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: add the missing AC97 pin configurationsEric Miao2010-03-0212-1/+74
| | | | | | | | | Missing AC97 pin configurations are added where pxa_set_ac97_info() are called for all pxa25x/pxa27x platforms. Where no exact configuration is provided, use the default as in sound/arm/pxa2xx-ac97-lib.c Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: introduce processor specific pxa27x_assert_ac97reset()Eric Miao2010-03-021-0/+19
| | | | | | | | | This is really pxa27x specific and should be kept in pxa27x.c. With this newly introduced function, the original set_resetgpio_mode() is deprecated. Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: simplify the LCD pin configuration for pxa27x platformsEric Miao2010-03-0214-257/+41
| | | | Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: simplify the LCD pin configuration for pxa25x platformsEric Miao2010-03-027-118/+38
| | | | | | | There are only limited possible LCD pin configurations for pxa25x platforms, simplify this by macro. Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: use chip->ack() instead of accessing GEDR directlyEric Miao2010-03-026-7/+6
| | | | Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* Merge branch 'for-rmk' of git://git.marvell.com/orion into devel-stableRussell King2010-02-2553-294/+1616
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| * [ARM] MV78xx0: Support for Buffalo WXL (Terastation Duo)Sebastien Requiem2010-02-234-0/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Modification of Kconfig to add the Option * 1 new file : buffalo-wxl-setup.c This file is inspired from the db-78xx0-setup.c already present. The following is done: - Configure MPP Lines for the plateform (see my patch for MPP) This is taken from the stock kernel provided by buffalotech (the vendor) - GigaBit Ethernet - Sata - Uart are initiallized in a different way than on the dev board as we have one core only. - USB The kernel has been running for some days now on my plateform. Signed-off-by: Sebastien Requiem <sebastien@kolios.dk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * [ARM] MV78XX0: MPP routines and definitionsSebastien Requiem2010-02-233-1/+444
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is composed of two new files : - mpp.c which is mainly inspired by the same file as in mach-kirkwood - mpp.h that is written from the documentation provided by Marvell http://www.marvell.com/products/processors/embedded/discovery_innovation/HW_MV78100_OpenSource.pdf Moreover, due to some implementation problem, I have defined some MPPX_UNUSED that offer developers the possibility to SET MPP to some unused value (such as for Buffalo WXL). Note: This patch doesn't support MV78200 yet (only 78100 MPP lines have been written) Signed-off-by: Sebastien Requiem <sebastien@kolios.dk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * [ARM] eSATA SheevaPlug: correlate MPP to SD CD and SD WPJohn Holland2010-02-231-2/+24
| | | | | | | | | | | | | | | | | | | | Accept SD CD and SD WP in accordance to http://plugcomputer.org/data/docs/Sheeva-PowerPlug-V1.3-GTI-090906.pdf on MPP 47 and 44 respectively on the eSATA SheevaPlug Signed-off-by: John Holland <john.holland@cellent-fs.de> Signed-off-by: Nicolas Pitre <nico@marvell.com> --
| * [ARM] eSATA SheevaPlug: configure SoC SATA interfaceJohn Holland2010-02-231-0/+10
| | | | | | | | | | | | | | | | Enable the kirkwood SATA SoC interface on the eSATA SheevaPlug. Signed-off-by: John Holland <john.holland@cellent-fs.de> Signed-off-by: Nicolas Pitre <nico@marvell.com> --
| * [ARM] eSATA SheevaPlug basic board supportJohn Holland2010-02-233-0/+21
| | | | | | | | | | | | | | | | Allow basic eSATA SheevaPlug board configuration and build. Signed-off-by: John Holland <john.holland@cellent-fs.de> Signed-off-by: Nicolas Pitre <nico@marvell.com> --
| * ARM: Update mach-typesRussell King2010-02-201-2/+44
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5950/1: ARM: Fix build error for arm1026ej-s processorAbdoulaye Walsimou Gaye2010-02-201-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fix the below build error for arm1026ej-s processor (IntegratorCP/arm1026ej-s board). CC init/main.o In file included from include/linux/highmem.h:8, from include/linux/pagemap.h:10, from include/linux/mempolicy.h:62, from init/main.c:52: arch/arm/include/asm/cacheflush.h:134:2: error: #error Unknown cache maintainence model make[1]: *** [init/main.o] Erreur 1 make: *** [init] Erreur 2 Signed-off-by: Abdoulaye Walsimou Gaye <walsimou@walsimou.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * Merge branch 'for-rmk' of git://gitorious.org/linux-gemini/mainlineRussell King2010-02-185-13/+24
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| | * Gemini: wrong registers used to set reg_level in gpio_set_irq_type()Roel Kluin2010-02-181-2/+2
| | | | | | | | | | | | | | | | | | | | | It appears the wrong GPIO registers were used Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Paulius Zaleckas <paulius.zaleckas@gmail.com>
| | * Merge branch 'release' of ↵Linus Torvalds2010-02-182-8/+1
| | |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6 * 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6: ACPI: fix "acpi=ht" boot option ACPI, i915: blacklist Clevo M5x0N bad_lid state ACPI: fix High cpu temperature with 2.6.32 ACPI: dock: properly initialize local struct dock_station in dock_add() ACPI: remove Asus P2B-DS from acpi=ht blacklist thinkpad-acpi: wrong thermal attribute_group removed in thermal_exit() ACPI: acpi_bus_{scan,bus,add}: return -ENODEV if no device was found ACPI: Add NULL pointer check in acpi_bus_start ACPI: processor: only evaluate _PDC once per processor ACPI: processor: add kernel command line support for early _PDC eval
| | | *-----. Merge branches 'bugzilla-14886', 'bugzilla-15000', 'bugzilla-15040', ↵Len Brown2010-02-182-8/+1
| | | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | 'bugzilla-15108', 'pdc', 'hotplug-null-ref' and 'thinkpad' into release
| | | | * | | | ACPI: fix "acpi=ht" boot optionLen Brown2010-02-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We broke "acpi=ht" in 2.6.32 by disabling MADT parsing for acpi=disabled. e5b8fc6ac158f65598f58dba2c0d52ba3b412f52 This also broke systems which invoked acpi=ht via DMI blacklist. acpi=ht is a really ugly hack, but restore it for those that still use it. http://bugzilla.kernel.org/show_bug.cgi?id=14886 Signed-off-by: Len Brown <len.brown@intel.com>
| | | | * | | | ACPI: remove Asus P2B-DS from acpi=ht blacklistLen Brown2010-02-161-8/+0
| | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We realized when we broke acpi=ht http://bugzilla.kernel.org/show_bug.cgi?id=14886 that acpi=ht is not needed on this box and folks have been using acpi=force on it anyway. Signed-off-by: Len Brown <len.brown@intel.com>
| | * | | | | Merge branch 'merge' of ↵Linus Torvalds2010-02-182-3/+21
| | |\ \ \ \ \ | | | |/ / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc * 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc/85xx: Fix SMP when "cpu-release-addr" is in lowmem powerpc/85xx: Fix oops during MSI driver probe on MPC85xxMDS boards
| | | * | | | powerpc/85xx: Fix SMP when "cpu-release-addr" is in lowmemPeter Tyser2010-02-131-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recent U-Boot commit 5ccd29c3679b3669b0bde5c501c1aa0f325a7acb caused the "cpu-release-addr" device tree property to contain the physical RAM location that secondary cores were spinning at. Previously, the "cpu-release-addr" property contained a value referencing the boot page translation address range of 0xfffffxxx, which then indirectly accessed RAM. The "cpu-release-addr" is currently ioremapped and the secondary cores kicked. However, due to the recent change in "cpu-release-addr", it sometimes points to a memory location in low memory that cannot be ioremapped. For example on a P2020-based board with 512MB of RAM the following error occurs on bootup: <...> mpic: requesting IPIs ... __ioremap(): phys addr 0x1ffff000 is RAM lr c05df9a0 Unable to handle kernel paging request for data at address 0x00000014 Faulting instruction address: 0xc05df9b0 Oops: Kernel access of bad area, sig: 11 [#1] SMP NR_CPUS=2 P2020 RDB Modules linked in: <... eventual kernel panic> Adding logic to conditionally ioremap or access memory directly resolves the issue. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Nate Case <ncase@xes-inc.com> Reported-by: Dipen Dudhat <B09055@freescale.com> Tested-by: Dipen Dudhat <B09055@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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