| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | x86, irq: Keep balance of IOAPIC pin reference count | Jiang Liu | 2014-12-16 | 1 | -1/+9 |
| * | x86, irq, PCI: Keep IRQ assignment for runtime power management | Jiang Liu | 2014-08-29 | 1 | -1/+1 |
| * | x86, irq, PCI: Keep IRQ assignment for PCI devices during suspend/hibernation | Jiang Liu | 2014-08-08 | 1 | -1/+1 |
| * | x86, irq, SFI: Release IOAPIC pin when PCI device is disabled | Jiang Liu | 2014-06-21 | 1 | -0/+7 |
| * | x86, irq, SFI: Use common irqdomain map interface to program IOAPIC pins | Jiang Liu | 2014-06-21 | 1 | -12/+7 |
| * | x86, SFI, irq: Provide basic irqdomain support | Jiang Liu | 2014-06-21 | 1 | -0/+3 |
| * | x86, intel-mid: Add Merrifield platform support | David Cohen | 2014-01-15 | 1 | -1/+5 |
| * | intel_mid: Renamed *mrst* to *intel_mid* | Kuppuswamy Sathyanarayanan | 2013-10-17 | 1 | -6/+6 |
| * | pci: intel_mid: Return true/false in function returning bool | Fengguang Wu | 2013-10-17 | 1 | -3/+3 |
| * | intel_mid: Renamed *mrst* to *intel_mid* | Kuppuswamy Sathyanarayanan | 2013-10-17 | 1 | -0/+310 |
