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* x86: add cpu mtrr init function definitions to mtrr.hHarvey Harrison2008-02-042-4/+4
| | | | | | | | | | | | | | mtrr.h was included everywhere needed. Fixes the following sparse warnings. Also, the return types in the extern definitions were incorrect. arch/x86/kernel/cpu/mtrr/amd.c:113:12: warning: symbol 'amd_init_mtrr' was not declared. Should it be static? arch/x86/kernel/cpu/mtrr/cyrix.c:268:12: warning: symbol 'cyrix_init_mtrr' was not declared. Should it be static? arch/x86/kernel/cpu/mtrr/centaur.c:218:12: warning: symbol 'centaur_init_mtrr' was not declared. Should it be static? Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: add cpu init function defintions to cpu.hHarvey Harrison2008-02-042-10/+9
| | | | | | | | | | | | | | | | | | | cpu.h was already included everywhere needed. Fixes following sparse warnings: arch/x86/kernel/cpu/amd.c:343:12: warning: symbol 'amd_init_cpu' was not declared. Should it be static? arch/x86/kernel/cpu/cyrix.c:444:12: warning: symbol 'cyrix_init_cpu' was not declared. Should it be static? arch/x86/kernel/cpu/cyrix.c:456:12: warning: symbol 'nsc_init_cpu' was not declared. Should it be static? arch/x86/kernel/cpu/centaur.c:467:12: warning: symbol 'centaur_init_cpu' was not declared. Should it be static? arch/x86/kernel/cpu/transmeta.c:112:12: warning: symbol 'transmeta_init_cpu' was not declared. Should it be static? arch/x86/kernel/cpu/intel.c:296:12: warning: symbol 'intel_cpu_init' was not declared. Should it be static? arch/x86/kernel/cpu/nexgen.c:56:12: warning: symbol 'nexgen_init_cpu' was not declared. Should it be static? arch/x86/kernel/cpu/umc.c:22:12: warning: symbol 'umc_init_cpu' was not declared. Should it be static? Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: add include to cpu/intel.cHarvey Harrison2008-02-041-0/+1
| | | | | | | | | | Fixes sparse warning: arch/x86/kernel/cpu/intel.c:48:15: warning: symbol 'ppro_with_ram_bug' was not declared. Should it be static? Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: remove long dead cyrix mtrr codeHarvey Harrison2008-02-042-119/+0
| | | | | | | | | | | cyrix_arr_init was #if 0 all the way back to at least v2.6.12. This was the only place where arr3_protected was set to anything but zero. Eliminate this variable. Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: unify CPU feature string namesH. Peter Anvin2008-02-043-74/+84
| | | | | | | | | | | Move the CPU feature string names to a separate file (common to 32 and 64 bits); additionally, make <asm/cpufeature.h> includable by host code in preparation for including the CPU feature strings in the boot code. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: fix bootup crash in native_read_tsc()Ingo Molnar2008-02-021-1/+1
| | | | | | | | | | fix bootup crash in native_read_tsc() that was reported on an Athlon-XP and bisected. The correct feature boundary for X86_FEATURE_MFENCE_RDTSC is not XMM but XMM2. Signed-off-by: Ingo Molnar <mingo@elte.hu> Acked-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* x86: fix sparse warnings in cpu/common.cHarvey Harrison2008-02-011-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The casts will always be needed, may as well make them the right signedness. The ebx variables can easily be unsigned, may as well. arch/x86/kernel/cpu/common.c:261:21: warning: incorrect type in argument 2 (different signedness) arch/x86/kernel/cpu/common.c:261:21: expected unsigned int *eax arch/x86/kernel/cpu/common.c:261:21: got int *<noident> arch/x86/kernel/cpu/common.c:262:9: warning: incorrect type in argument 3 (different signedness) arch/x86/kernel/cpu/common.c:262:9: expected unsigned int *ebx arch/x86/kernel/cpu/common.c:262:9: got int *<noident> arch/x86/kernel/cpu/common.c:263:9: warning: incorrect type in argument 4 (different signedness) arch/x86/kernel/cpu/common.c:263:9: expected unsigned int *ecx arch/x86/kernel/cpu/common.c:263:9: got int *<noident> arch/x86/kernel/cpu/common.c:264:9: warning: incorrect type in argument 5 (different signedness) arch/x86/kernel/cpu/common.c:264:9: expected unsigned int *edx arch/x86/kernel/cpu/common.c:264:9: got int *<noident> arch/x86/kernel/cpu/common.c:293:30: warning: incorrect type in argument 3 (different signedness) arch/x86/kernel/cpu/common.c:293:30: expected unsigned int *ebx arch/x86/kernel/cpu/common.c:293:30: got int *<noident> arch/x86/kernel/cpu/common.c:350:22: warning: incorrect type in argument 2 (different signedness) arch/x86/kernel/cpu/common.c:350:22: expected unsigned int *eax arch/x86/kernel/cpu/common.c:350:22: got int *<noident> arch/x86/kernel/cpu/common.c:351:10: warning: incorrect type in argument 3 (different signedness) arch/x86/kernel/cpu/common.c:351:10: expected unsigned int *ebx arch/x86/kernel/cpu/common.c:351:10: got int *<noident> arch/x86/kernel/cpu/common.c:352:10: warning: incorrect type in argument 4 (different signedness) arch/x86/kernel/cpu/common.c:352:10: expected unsigned int *ecx arch/x86/kernel/cpu/common.c:352:10: got int *<noident> arch/x86/kernel/cpu/common.c:353:10: warning: incorrect type in argument 5 (different signedness) arch/x86/kernel/cpu/common.c:353:10: expected unsigned int *edx arch/x86/kernel/cpu/common.c:353:10: got int *<noident> arch/x86/kernel/cpu/common.c:362:30: warning: incorrect type in argument 3 (different signedness) arch/x86/kernel/cpu/common.c:362:30: expected unsigned int *ebx arch/x86/kernel/cpu/common.c:362:30: got int *<noident> Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: c_p_a clflush_cache_range fixHuang, Ying2008-01-311-1/+4
| | | | | | | | | | Because in i386 early boot stage, boot_cpu_data may be not available, which makes clflush_cach_range() into infinite loop, which is called by change_page_attr(). This patch fixes this by setting boot_cpu_data.x86_clflush_size in early_cpu_detect(). Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: fix sparse warnings in intel_cacheinfo.cHarvey Harrison2008-01-311-3/+3
| | | | | | | | | | | | | | | | | | | | arch/x86/kernel/cpu/intel_cacheinfo.c:355:7: warning: symbol 'i' shadows an earlier one arch/x86/kernel/cpu/intel_cacheinfo.c:296:39: originally declared here arch/x86/kernel/cpu/intel_cacheinfo.c:367:18: warning: incorrect type in argument 2 (different signedness) arch/x86/kernel/cpu/intel_cacheinfo.c:367:18: expected unsigned int *eax arch/x86/kernel/cpu/intel_cacheinfo.c:367:18: got int * arch/x86/kernel/cpu/intel_cacheinfo.c:367:28: warning: incorrect type in argument 3 (different signedness) arch/x86/kernel/cpu/intel_cacheinfo.c:367:28: expected unsigned int *ebx arch/x86/kernel/cpu/intel_cacheinfo.c:367:28: got int * arch/x86/kernel/cpu/intel_cacheinfo.c:367:38: warning: incorrect type in argument 4 (different signedness) arch/x86/kernel/cpu/intel_cacheinfo.c:367:38: expected unsigned int *ecx arch/x86/kernel/cpu/intel_cacheinfo.c:367:38: got int * arch/x86/kernel/cpu/intel_cacheinfo.c:367:48: warning: incorrect type in argument 5 (different signedness) arch/x86/kernel/cpu/intel_cacheinfo.c:367:48: expected unsigned int *edx arch/x86/kernel/cpu/intel_cacheinfo.c:367:48: got int * Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: do not PSE on CONFIG_DEBUG_PAGEALLOC=yIngo Molnar2008-01-301-7/+0
| | | | | | | | | | | | | | get more testing of the c_p_a() code done by not turning off PSE on DEBUG_PAGEALLOC. this simplifies the early pagetable setup code, and tests the largepage-splitup code quite heavily. In the end, all the largepages will be split up pretty quickly, so there's no difference to how DEBUG_PAGEALLOC worked before. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: fix recursion in arch/x86/kernel/cpu/mcheck/mce_amd_64.cYinghai Lu2008-01-301-2/+2
| | | | | | | remove the recursion from this function. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: fix section mismatch warning in mcheck/mce_amd_64.cSam Ravnborg2008-01-301-2/+2
| | | | | | | | | | | | | | | Fix following warning: WARNING: arch/x86/kernel/cpu/mcheck/built-in.o(.text+0x1584): Section mismatch: reference to .cpuinit.text:threshold_create_device in 'threshold_cpu_callback' threshold_cpu_callback() is only used by threshold_cpu_notifier. threshold_cpu_notifier is only used for cpu hot plug as it is registered using register_hotcpu_notifier(). Mark them both __cpuinit to fix the warning. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: fix section mismatch warning in mcheck/mce_64.cSam Ravnborg2008-01-301-3/+3
| | | | | | | | | | | | | | | Fix following warning: WARNING: arch/x86/kernel/cpu/mcheck/built-in.o(.text+0x752): Section mismatch: reference to .cpuinit.text:mce_create_device in 'mce_cpu_callback' mce_cpu_callback() is only used by mce_cpu_notofier. The notifier is only used for hotplugable cpu's as it is registered using register_hotcpu_notifier(), Annotate them both __cpuinit to fix the warning. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: improve MTRR trimming messagesIngo Molnar2008-01-301-10/+7
| | | | | | | | improve the MTTR trimming messages and also trigger a WARN_ON() so that kerneloops.org can pick it up and categorize it. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86_32: trim memory by updating e820Yinghai Lu2008-01-302-9/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when MTRRs are not covering the whole e820 table, we need to trim the RAM and need to update e820. reuse some code on 64-bit as well. here need to add early_get_cap and use it in early_cpu_detect, and move mtrr_bp_init early. The code successfully trimmed the memory map on Justin's system: from: [ 0.000000] BIOS-e820: 0000000100000000 - 000000022c000000 (usable) to: [ 0.000000] modified: 0000000100000000 - 0000000228000000 (usable) [ 0.000000] modified: 0000000228000000 - 000000022c000000 (reserved) According to Justin it makes quite a difference: | When I boot the box without any trimming it acts like a 286 or 386, | takes about 10 minutes to boot (using raptor disks). Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Tested-by: Justin Piszcz <jpiszcz@lucidpixels.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: constify function pointer tablesJan Engelhardt2008-01-301-1/+1
| | | | | | Signed-off-by: Jan Engelhardt <jengelh@computergmbh.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: remove unneded castsJan Engelhardt2008-01-301-1/+1
| | | | | | | | x86: remove unneeded casts Signed-off-by: Jan Engelhardt <jengelh@computergmbh.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: add generic clearcpuid=... optionAndi Kleen2008-01-301-0/+11
| | | | | | | | | | Add a generic option to clear any cpuid bit. I added it because it was very easy to add with the new generic cpuid disable bitmap and perhaps it will be useful in the future. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: add noclflush optionAndi Kleen2008-01-301-0/+7
| | | | | | | | To disable CLFLUSH usage, especially in change_page_attr(). Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: convert TSC disabling to generic cpuid disable bitmapAndi Kleen2008-01-302-10/+1
| | | | | | | | Fix from: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: don't disable RDTSC in userland for 32bit notscAndi Kleen2008-01-301-1/+0
| | | | | | | | | | Modern 32bit userland doesn't even boot when the TSC is disabled because ld.so tends to contain RDTSCs. So make notsc only effective for the kernel, similar to 64bit. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: convert some existing cpuid disable options to new generic bitmapAndi Kleen2008-01-301-30/+4
| | | | | | | | | This convers nofxsr, mem=nopentium and nosep to use the new generic cpuid disable bitmap instead of using own variables. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: add framework to disable CPUID bits on the command lineAndi Kleen2008-01-301-0/+6
| | | | | | | | | | There are already various options to disable specific cpuid bits on the command line. They all use their own variable. Add a generic mask to make this easier in the future. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86, 32-bit: trim memory not covered by wb mtrrsJesse Barnes2008-01-304-37/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some machines, buggy BIOSes don't properly setup WB MTRRs to cover all available RAM, meaning the last few megs (or even gigs) of memory will be marked uncached. Since Linux tends to allocate from high memory addresses first, this causes the machine to be unusably slow as soon as the kernel starts really using memory (i.e. right around init time). This patch works around the problem by scanning the MTRRs at boot and figuring out whether the current end_pfn value (setup by early e820 code) goes beyond the highest WB MTRR range, and if so, trimming it to match. A fairly obnoxious KERN_WARNING is printed too, letting the user know that not all of their memory is available due to a likely BIOS bug. Something similar could be done on i386 if needed, but the boot ordering would be slightly different, since the MTRR code on i386 depends on the boot_cpu_data structure being setup. This patch fixes a bug in the last patch that caused the code to run on non-Intel machines (AMD machines apparently don't need it and it's untested on other non-Intel machines, so best keep it off). Further enhancements and fixes from: Yinghai Lu <Yinghai.Lu@Sun.COM> Andi Kleen <ak@suse.de> Signed-off-by: Jesse Barnes <jesse.barnes@intel.com> Tested-by: Justin Piszcz <jpiszcz@lucidpixels.com> Cc: Andi Kleen <andi@firstfloor.org> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Cc: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: use the correct cpuid method to detect MWAIT support for C statesAndi Kleen2008-01-301-3/+0
| | | | | | | | | | | | | | | | | | | | Previously there was a AMD specific quirk to handle the case of AMD Fam10h MWAIT not supporting any C states. But it turns out that CPUID already has ways to detectly detect that without using special quirks. The new code simply checks if MWAIT supports at least C1 and doesn't use it if it doesn't. No more vendor specific code. Note this is does not simply clear MWAIT because MWAIT can be still useful even without C states. Credit goes to Ben Serebrin for pointing out the (nearly) obvious. Cc: "Andreas Herrmann" <andreas.herrmann3@amd.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: move MWAIT idle check to generic CPU initialization on 32-bitAndi Kleen2008-01-302-1/+2
| | | | | | | | | | Previously it was only run for Intel CPUs, but AMD Fam10h implements MWAIT too. This matches 64bit behaviour. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: change NR_CPUS arrays in acpi-cpufreqtravis@sgi.com2008-01-301-12/+13
| | | | | | | | | | | | Change the following static arrays sized by NR_CPUS to per_cpu data variables: acpi_cpufreq_data *drv_data[NR_CPUS] Signed-off-by: Mike Travis <travis@sgi.com> Reviewed-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: change NR_CPUS arrays in powernow-k8travis@sgi.com2008-01-301-6/+6
| | | | | | | | | | | | Change the following static arrays sized by NR_CPUS to per_cpu data variables: powernow_k8_data *powernow_data[NR_CPUS]; Signed-off-by: Mike Travis <travis@sgi.com> Reviewed-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: change x86 machine check handler to use unlocked_ioctl insteadNikanth Karthikesan2008-01-301-3/+2
| | | | | | | | | | | | | | | | | | The machine check handler registers ioctl handler that is called with the BKL held. Changing to register unlocked_ioctl instead. Also mce ioctl handler does not seem to need any lock protection. To: Andi Kleen <andi@firstfloor.org> Cc: linux-kernel@vger.kernel.org Cc: kernel-janitors@vger.kernel.org Change the Machine check handler to use unlocked_ioctl instead of ioctl handler. Also the mce ioctl handler does not need any lock protection. Signed-off-by: Nikanth Karthikesan <knikanth@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: remove CPU capabitilites printks on 32-bitAndi Kleen2008-01-301-19/+1
| | | | | | | | I don't know of any case where they have been useful and they look ugly. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: move X86_FEATURE_CONSTANT_TSC into early cpu feature detectionAndi Kleen2008-01-304-16/+28
| | | | | | | | | | | | Need this in the next patch in time_init and that happens early. This includes a minor fix on i386 where early_intel_workarounds() [which is now called early_init_intel] really executes early as the comments say. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: lfence fixIngo Molnar2008-01-301-1/+1
| | | | | | | | | LFENCE is available on XMM2 or higher Intel CPUs - not XMM or higher... this caused boot failures on XMM1 & !XMM1 capable CPUs. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: Implement support to synchronize RDTSC with LFENCE on Intel CPUsAndi Kleen2008-01-301-1/+2
| | | | | | | | | | | | | According to Intel RDTSC can be always synchronized with LFENCE on all current CPUs. Implement the necessary CPUID bit for that. It is unclear yet if that is true for all future CPUs too, but if there's another way the kernel can be always updated. Cc: asit.k.mallick@intel.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: implement support to synchronize RDTSC through MFENCE on AMD CPUsAndi Kleen2008-01-301-0/+3
| | | | | | | | | | According to AMD RDTSC can be synchronized through MFENCE. Implement the necessary CPUID bit for that. Cc: andreas.herrmann3@amd.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: arch/x86/kernel/cpu/mcheck/k7.c checkpatch fixesAndrew Morton2008-01-303-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | #88: FILE: arch/x86/kernel/cpu/mcheck/k7.c:34: + rdmsr(MSR_IA32_MC0_STATUS+i*4,low, high); ^ ERROR: need space after that ',' (ctx:VxV) #142: FILE: arch/x86/kernel/cpu/mcheck/p4.c:170: + rdmsr(MSR_IA32_MC0_STATUS+i*4,low, high); ^ ERROR: need space after that ',' (ctx:VxV) #180: FILE: arch/x86/kernel/cpu/mcheck/p6.c:34: + rdmsr(MSR_IA32_MC0_STATUS+i*4,low, high); ^ total: 3 errors, 0 warnings, 114 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Please run checkpatch prior to sending patches Cc: Min Zhang <mzhang@mvista.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: arch/x86/kernel/cpu/mcheck/ checkpatch fixesAndrew Morton2008-01-303-26/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | #40: FILE: arch/x86/kernel/cpu/mcheck/k7.c:46: + snprintf (misc, 20, "[%08x%08x]", ahigh, alow); WARNING: line over 80 characters #45: FILE: arch/x86/kernel/cpu/mcheck/k7.c:50: + snprintf (addr, 24, " at %08x%08x", ahigh, alow); WARNING: no space between function name and open parenthesis '(' #45: FILE: arch/x86/kernel/cpu/mcheck/k7.c:50: + snprintf (addr, 24, " at %08x%08x", ahigh, alow); WARNING: no space between function name and open parenthesis '(' #48: FILE: arch/x86/kernel/cpu/mcheck/k7.c:52: + printk (KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n", WARNING: no space between function name and open parenthesis '(' #65: FILE: arch/x86/kernel/cpu/mcheck/p4.c:161: + printk (KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n" WARNING: no space between function name and open parenthesis '(' #88: FILE: arch/x86/kernel/cpu/mcheck/p4.c:182: + snprintf (misc, 20, "[%08x%08x]", ahigh, alow); WARNING: line over 80 characters #93: FILE: arch/x86/kernel/cpu/mcheck/p4.c:186: + snprintf (addr, 24, " at %08x%08x", ahigh, alow); WARNING: no space between function name and open parenthesis '(' #93: FILE: arch/x86/kernel/cpu/mcheck/p4.c:186: + snprintf (addr, 24, " at %08x%08x", ahigh, alow); WARNING: no space between function name and open parenthesis '(' #96: FILE: arch/x86/kernel/cpu/mcheck/p4.c:188: + printk (KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n", WARNING: no space between function name and open parenthesis '(' #120: FILE: arch/x86/kernel/cpu/mcheck/p6.c:46: + snprintf (misc, 20, "[%08x%08x]", ahigh, alow); WARNING: line over 80 characters #125: FILE: arch/x86/kernel/cpu/mcheck/p6.c:50: + snprintf (addr, 24, " at %08x%08x", ahigh, alow); WARNING: no space between function name and open parenthesis '(' #125: FILE: arch/x86/kernel/cpu/mcheck/p6.c:50: + snprintf (addr, 24, " at %08x%08x", ahigh, alow); WARNING: no space between function name and open parenthesis '(' #128: FILE: arch/x86/kernel/cpu/mcheck/p6.c:52: + printk (KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n", total: 0 errors, 13 warnings, 100 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Please run checkpatch prior to sending patches Cc: Min Zhang <mzhang@mvista.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* arch/x86/kernel/cpu/mcheck/p4.c: cleanupsMin Zhang2008-01-303-17/+26
| | | | | | | | | | | | | SMP, the machine check exception dispatches all logical processors within a physical package to the machine-check exception handler, so the printk within each handler outputs concurrently and makes the output unreadable. Refer to Intel system programming guide Part 1 Section 7.8.5 http://developer.intel.com/design/processor/manuals/253668.pdf Signed-off-by: Min Zhang <mzhang@mvista.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: move definitions to processor.hGlauber de Oliveira Costa2008-01-301-1/+1
| | | | | | | | | | This patch moves definitions that are present in only one of the files (between processor_32.h and processor_64.h), to processor.h. They're mostly structures and function definitions. Signed-off-by: Glauber de Oliveira Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: unify x86_cpuinfo struct.Glauber de Oliveira Costa2008-01-301-3/+3
| | | | | | | | | | x86_cpuinfo is one more to the family of "not fundamentally different" structs. It's unified in processor.h, with very specific fields enclosed around ifdefs. Signed-off-by: Glauber de Oliveira Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86-64: honor notify_die() returning NOTIFY_STOPJan Beulich2008-01-301-4/+4
| | | | | | | | | | This requires making die() return a value, making its callers honor this (and be prepared that it may return), and making oops_end() have two additional parameters. Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* mcheck mce_64: mce_read_sem to mutexDaniel Walker2008-01-301-4/+4
| | | | | | | | | Converted to a mutex, and changed the name to mce_read_mutex. Signed-off-by: Daniel Walker <dwalker@mvista.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: remove all definitions with fastcallHarvey Harrison2008-01-307-9/+9
| | | | | | | | fastcall is always defined to be empty, remove it from arch/x86 Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: unify struct desc_ptrGlauber de Oliveira Costa2008-01-301-1/+1
| | | | | | | | | | | | | | This patch unifies struct desc_ptr between i386 and x86_64. They can be expressed in the exact same way in C code, only having to change the name of one of them. As Xgt_desc_struct is ugly and big, this is the one that goes away. There's also a padding field in i386, but it is not really needed in the C structure definition. Signed-off-by: Glauber de Oliveira Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: unify desc_structGlauber de Oliveira Costa2008-01-301-14/+21
| | | | | | | | | | | | | | | | | | This patch aims to make the access of struct desc_struct variables equal across architectures. In this patch, I unify the i386 and x86_64 versions under an anonymous union, keeping the way they are accessed untouched (a and b for 32-bit code, individual bit-fields for 64-bit). This solution is not beautiful, but will allow us to integrate common code that differed by the way descriptors were used. This is to be viewed incrementally. There's simply too much code to be fixed at once. In the future, goal is to set up in a single way of acessing the desc_struct fields. Signed-off-by: Glauber de Oliveira Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86, ptrace: support for branch trace store(BTS)Markus Metzger2008-01-301-0/+5
| | | | | | | | | | | | | | | Resend using different mail client Changes to the last version: - split implementation into two layers: ds/bts and ptrace - renamed TIF's - save/restore ds save area msr in __switch_to_xtra() - make block-stepping only look at BTF bit Signed-off-by: Markus Metzger <markus.t.metzger@intel.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: use generic register name in the thread and tss structuresH. Peter Anvin2008-01-301-1/+1
| | | | | | | | | This changes size-specific register names (eip/rip, esp/rsp, etc.) to generic names in the thread and tss structures. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: rename the struct pt_regs members for 32/64-bit consistencyH. Peter Anvin2008-01-302-8/+8
| | | | | | | | | | | | | | | We have a lot of code which differs only by the naming of specific members of structures that contain registers. In order to enable additional unifications, this patch drops the e- or r- size prefix from the register names in struct pt_regs, and drops the x- prefixes for segment registers on the 32-bit side. This patch also performs the equivalent renames in some additional places that might be candidates for unification in the future. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: add set/clear_cpu_cap operationsJeremy Fitzhardinge2008-01-302-2/+2
| | | | | | | | | | | | | The patch to suppress bitops-related warnings added a pile of ugly casts. Many of these were related to the management of x86 CPU capabilities. Clean these up by adding specific set/clear_cpu_cap macros, and use them consistently. Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: fall back on interrupt disable in cmpxchg8b on 80386 and 80486Mathieu Desnoyers2008-01-301-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Actually, on 386, cmpxchg and cmpxchg_local fall back on cmpxchg_386_u8/16/32: it disables interruptions around non atomic updates to mimic the cmpxchg behavior. The comment: /* Poor man's cmpxchg for 386. Unsuitable for SMP */ already present in cmpxchg_386_u32 tells much about how this cmpxchg implementation should not be used in a SMP context. However, the cmpxchg_local can perfectly use this fallback, since it only needs to be atomic wrt the local cpu. This patch adds a cmpxchg_486_u64 and uses it as a fallback for cmpxchg64 and cmpxchg64_local on 80386 and 80486. Q: but why is it called cmpxchg_486 when the other functions are called A: Because the standard cmpxchg is missing only on 386, but cmpxchg8b is missing both on 386 and 486. Citing Intel's Instruction set reference: cmpxchg: This instruction is not supported on Intel processors earlier than the Intel486 processors. cmpxchg8b: This instruction encoding is not supported on Intel processors earlier than the Pentium processors. Q: What's the reason to have cmpxchg64_local on 32 bit architectures? Without that need all this would just be a few simple defines. A: cmpxchg64_local on 32 bits architectures takes unsigned long long parameters, but cmpxchg_local only takes longs. Since we have cmpxchg8b to execute a 8 byte cmpxchg atomically on pentium and +, it makes sense to provide a flavor of cmpxchg and cmpxchg_local using this instruction. Also, for 32 bits architectures lacking the 64 bits atomic cmpxchg, it makes sense _not_ to define cmpxchg64 while cmpxchg could still be available. Moreover, the fallback for cmpxchg8b on i386 for 386 and 486 is a However, cmpxchg64_local will be emulated by disabling interrupts on all architectures where it is not supported atomically. Therefore, we *could* turn cmpxchg64_local into a cmpxchg_local, but it would make the 386/486 fallbacks ugly, make its design different from cmpxchg/cmpxchg64 (which really depends on atomic operations and cannot be emulated) and require the __cmpxchg_local to be expressed as a macro rather than an inline function so the parameters would not be fixed to unsigned long long in every case. So I think cmpxchg64_local makes sense there, but I am open to suggestions. Q: Are there any callers? A: I am actually using it in LTTng in my timestamping code. I use it to work around CPUs with asynchronous TSCs. I need to update 64 bits values atomically on this 32 bits architecture. Changelog: - Ran though checkpatch. Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: extended interrupt LVT support for AMD BarcelonaRobert Richter2008-01-301-5/+5
| | | | | | | Also macro definitions in apicdef.h has been updated. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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