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path: root/arch/x86/kernel/cpu/perf_event_intel.c
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* perf/x86: Fix shared register mutual exclusion enforcementStephane Eranian2013-06-261-2/+0
* perf/x86/intel: Support full width countingAndi Kleen2013-06-261-0/+7
* perf/x86/intel: Add mem-loads/stores support for HaswellAndi Kleen2013-06-191-0/+10
* perf/x86/intel: Move NMI clearing to end of PMI handlerAndi Kleen2013-06-191-8/+12
* perf/x86/intel: Add Haswell PEBS supportAndi Kleen2013-06-191-2/+4
* perf/x86/intel: Add simple Haswell PMU supportAndi Kleen2013-06-191-1/+84
* perf/x86: Only print PMU state when also WARN()'ingDave Hansen2013-06-191-2/+6
* perf/x86: Fix broken PEBS-LL support on SNB-EP/IVB-EPStephane Eranian2013-06-191-1/+1
* Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2013-05-051-4/+9
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| * perf/x86: Blacklist all MEM_*_RETIRED events for Ivy BridgePeter Zijlstra2013-05-041-4/+9
* | Merge branch 'perf/urgent' into perf/coreIngo Molnar2013-04-211-4/+17
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| * perf/x86: Fix offcore_rsp valid mask for SNB/IVBStephane Eranian2013-04-161-4/+16
* | perf/x86: Add Sandy Bridge constraints for CYCLE_ACTIVITY.*Andi Kleen2013-04-101-0/+2
* | perf/x86: Add support for PEBS Precise StoreStephane Eranian2013-04-011-0/+2
* | perf/x86: Export PEBS load latency threshold register to sysfsStephane Eranian2013-04-011-0/+3
* | perf/x86: Add memory profiling via PEBS Load LatencyStephane Eranian2013-04-011-0/+24
* | perf/x86: Add flags to event constraintsStephane Eranian2013-04-011-1/+5
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* perf/x86: Add SNB/SNB-EP scheduling constraints for cycle_activity eventStephane Eranian2013-03-181-0/+4
* perf/x86: Add Intel IvyBridge event scheduling constraintsStephane Eranian2013-02-201-1/+22
* x86/perf: Add IvyBridge EP supportYouquan Song2013-01-241-0/+1
* perf/x86: Enable Intel Lincroft/Penwell/Cloverview Atom supportShuoX Liu2013-01-241-1/+4
* perf/x86: Add hardware events translations for AMD cpusJiri Olsa2012-10-241-2/+9
* perf/x86: Add hardware events translations for Intel cpusJiri Olsa2012-10-241-0/+2
* perf/x86: Add support for Intel Xeon-Phi Knights Corner PMUVince Weaver2012-10-041-0/+2
* perf/x86: Fix Intel Ivy Bridge supportStephane Eranian2012-09-191-1/+23
* perf/x86: Enable Intel Cedarview Atom suppportStephane Eranian2012-09-041-0/+1
* perf/x86: disable PEBS on a guest entry.Gleb Natapov2012-08-131-1/+9
* perf/x86: Fix LLC-* and node-* events on Intel SandyBridgeYan, Zheng2012-07-261-6/+86
* Merge branch 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kern...Linus Torvalds2012-07-221-5/+7
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| * Merge commit 'v3.5-rc3' into x86/debugIngo Molnar2012-06-201-37/+108
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| | * perf/x86: Enable/Add IvyBridge hardware supportPeter Zijlstra2012-06-061-1/+2
| | * perf/x86: Implement cycles:p for SNB/IVBPeter Zijlstra2012-06-061-8/+42
| | * perf/x86: Fix Intel shared extra MSR allocationPeter Zijlstra2012-06-061-28/+64
| * | x86/debug: Add KERN_<LEVEL> to bare printks, convert printks to pr_<level>Joe Perches2012-06-061-6/+8
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* | perf/x86: Fix intel_perfmon_event_mapformattingPekka Enberg2012-07-061-8/+8
* | perf/x86: Add a microcode revision check for SNB-PEBSPeter Zijlstra2012-07-051-3/+48
* | perf/x86: Move Intel specific code to intel_pmu_init()Robert Richter2012-07-051-0/+33
* | perf/x86: Rename Intel specific macrosRobert Richter2012-07-051-7/+7
* | Merge branch 'x86/cpu' into perf/coreIngo Molnar2012-07-051-3/+3
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| * | x86, cpu: Rename checking_wrmsrl() to wrmsrl_safe()H. Peter Anvin2012-06-071-3/+3
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* | perf/x86: Don't assume there can be only 4 PEBS eventsAndi Kleen2012-06-061-0/+2
* | perf/x86: Enable/Add IvyBridge hardware supportPeter Zijlstra2012-06-061-1/+2
* | perf/x86: Implement cycles:p for SNB/IVBPeter Zijlstra2012-06-061-8/+42
* | perf/x86: Fix Intel shared extra MSR allocationPeter Zijlstra2012-06-061-28/+64
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* perf: Pass last sampling period to perf_sample_data_init()Robert Richter2012-05-091-3/+1
* perf: Adding sysfs group format attribute for pmu deviceJiri Olsa2012-03-161-0/+36
* Merge branch 'perf/hw-branch-sampling' into perf/coreIngo Molnar2012-03-121-27/+93
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| * perf: Add callback to flush branch_stack on context switchStephane Eranian2012-03-051-0/+13
| * perf/x86: Implement PERF_SAMPLE_BRANCH for Intel CPUsStephane Eranian2012-03-051-0/+35
| * perf/x86: Add Intel LBR mappings for PERF_SAMPLE_BRANCH filtersStephane Eranian2012-03-051-1/+1
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