summaryrefslogtreecommitdiffstats
path: root/arch/x86/kernel/amd_nb.c
Commit message (Expand)AuthorAgeFilesLines
* x86/gart: Check for GART support before accessing GART registersAravind Gopalakrishnan2015-05-061-3/+1
* x86, amd_nb: Add device IDs to NB tables for F15h M60hAravind Gopalakrishnan2014-10-201-0/+2
* Merge tag 'edac_for_3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bpLinus Torvalds2014-04-011-0/+2
|\
| * amd64_edac: Add support for newer F16h modelsAravind Gopalakrishnan2014-02-271-0/+2
* | x86/AMD/NB: Fix amd_set_subcaches() parameter typeDan Carpenter2014-01-251-1/+1
|/
* x86, amd_nb: Clarify F15h, model 30h GART and L3 supportAravind Gopalakrishnan2013-08-121-2/+11
* Merge branch 'x86-ras-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2013-04-301-1/+2
|\
| * amd64_edac: Add Family 16h supportAravind Gopalakrishnan2013-04-191-1/+2
* | x86: Constify a few itemsJan Beulich2013-03-111-1/+1
|/
* Merge branch 'x86-mce-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2012-07-221-0/+1
|\
| * x86, amd_nb: Export model 0x10 and later PCI idBorislav Petkov2012-06-071-0/+1
* | x86/debug: Add KERN_<LEVEL> to bare printks, convert printks to pr_<level>Joe Perches2012-06-061-4/+6
|/
* Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jb...Linus Torvalds2012-01-111-0/+31
|\
| * x86/PCI: amd: factor out MMCONFIG discoveryBjorn Helgaas2012-01-061-0/+31
* | x86: Simplify code by removing a !SMP #ifdefs from 'struct cpuinfo_x86'Kevin Winchester2011-12-211-6/+2
|/
* x86, amd-nb: Rename CPU PCI id define for F4Borislav Petkov2011-03-311-1/+1
* Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bpLinus Torvalds2011-03-171-1/+1
|\
| * PCI: Rename CPU PCI id defineBorislav Petkov2011-03-171-1/+1
* | x86, amd-nb: Misc cleanliness fixesBorislav Petkov2011-03-031-8/+10
* | x86: Adjust section placement in AMD northbridge related codeJan Beulich2011-02-101-3/+4
* | x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUsHans Rosenfeld2011-02-071-0/+63
* | x86, amd: Extend AMD northbridge caching code to support "Link Control" devicesHans Rosenfeld2011-01-261-2/+9
* | x86, amd: Enable L3 cache index disable on family 0x15Hans Rosenfeld2011-01-261-0/+3
|/
* x86: Use PCI method for enabling AMD extended config space before MSR methodJan Beulich2011-01-111-0/+7
* x86, cacheinfo: Cleanup L3 cache index disable supportHans Rosenfeld2010-11-181-0/+10
* x86, amd-nb: Cleanup AMD northbridge caching codeHans Rosenfeld2010-11-181-47/+62
* x86, amd-nb: Complete the rename of AMD NB and related codeHans Rosenfeld2010-11-181-36/+36
* x86, amd_nb: Enable GART support for AMD family 0x15 CPUsAndreas Herrmann2010-10-011-1/+3
* x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NBAndreas Herrmann2010-09-201-0/+145
OpenPOWER on IntegriCloud