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* [SPARC64]: Add some hypervisor tlb_type checks.David S. Miller2006-03-202-8/+30
| | | | | | | And more consistently check cheetah{,_plus} instead of assuming anything not spitfire is cheetah{,_plus}. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: SUN4V hypervisor TLB flush support code.David S. Miller2006-03-201-10/+214
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Refine register window trap handling.David S. Miller2006-03-206-439/+214
| | | | | | | | | | | When saving and restoing trap state, do the window spill/fill handling inline so that we never trap deeper than 2 trap levels. This is important for chips like Niagara. The window fixup code is massively simplified, and many more improvements are now possible. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add explicit register args to trap state loading macros.David S. Miller2006-03-205-27/+20
| | | | | | | This, as well as making the code cleaner, allows a simplification in the TSB miss handling path. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Refine code sequences to get the cpu id.David S. Miller2006-03-206-87/+73
| | | | | | | | | | | | | | | | | | On uniprocessor, it's always zero for optimize that. On SMP, the jmpl to the stub kills the return address stack in the cpu branch prediction logic, so expand the code sequence inline and use a code patching section to fix things up. This also always better and explicit register selection, which will be taken advantage of in a future changeset. The hard_smp_processor_id() function is big, so do not inline it. Fix up tests for Jalapeno to also test for Serrano chips too. These tests want "jbus Ultra-IIIi" cases to match, so that is what we should test for. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Turn off TSB growing for now.David S. Miller2006-03-202-15/+1
| | | | | | | | | | | | | | | | | | | | | | | | There are several tricky races involved with growing the TSB. So just use base-size TSBs for user contexts and we can revisit enabling this later. One part of the SMP problems is that tsb_context_switch() can see partially updated TSB configuration state if tsb_grow() is running in parallel. That's easily solved with a seqlock taken as a writer by tsb_grow() and taken as a reader to capture all the TSB config state in tsb_context_switch(). Then there is flush_tsb_user() running in parallel with a tsb_grow(). In theory we could take the seqlock as a reader there too, and just resample the TSB pointer and reflush but that looks really ugly. Lastly, I believe there is a case with threads that results in a TSB entry lock bit being set spuriously which will cause the next access to that TSB entry to wedge the cpu (since the TSB entry lock bit will never clear). It's either copy_tsb() or some bug elsewhere in the TSB assembly. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Correctable ECC errors cannot occur at trap level > 0.David S. Miller2006-03-202-18/+1
| | | | | | | | | | | | | The are distrupting, which by the sparc v9 definition means they can only occur when interrupts are enabled in the %pstate register. This never occurs in any of the trap handling code running at trap levels > 0. So just mark it as an unexpected trap. This allows us to kill off the cee_stuff member of struct thread_info. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Access TSB with physical addresses when possible.David S. Miller2006-03-207-47/+143
| | | | | | | | | | | | | This way we don't need to lock the TSB into the TLB. The trick is that every TSB load/store is registered into a special instruction patch section. The default uses virtual addresses, and the patch instructions use physical address load/stores. We can't do this on all chips because only cheetah+ and later have the physical variant of the atomic quad load. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Don't clobber alt-global %g4 on window fixups.David S. Miller2006-03-201-1/+1
| | | | | | | | If we are returning back to kernel mode, %g4 could be live (for example, in the case where we window spill in the etrap code). So do not change it's value if going back to kernel. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix race in LOAD_PER_CPU_BASE()David S. Miller2006-03-203-6/+6
| | | | | | | | | | Since we use %g5 itself as a temporary, it can get clobbered if we take an interrupt mid-stream and thus cause end up with the final %g5 value too early as a result of rtrap processing. Set %g5 at the very end, atomically, to avoid this problem. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill swapper_pgd_zero, totally unused.David S. Miller2006-03-201-3/+0
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix too early reference to %g6David S. Miller2006-03-201-2/+5
| | | | | | | | | %g6 is not necessarily set to current_thread_info() at sparc64_realfault_common. So store the fault code and address after we invoke etrap and %g6 is properly set up. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill hard-coded %pstate setting in sparc_exit.David S. Miller2006-03-201-2/+3
| | | | | | | Just flip the bit off of whatever it's currently set to. PSTATE_IE is guarenteed to be enabled when we get here. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Increase swapper_tsb size to 32K.David S. Miller2006-03-203-17/+6
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill sole argument passed to setup_tba().David S. Miller2006-03-202-10/+3
| | | | | | No longer used, and move extern declaration to a header file. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill PROM locked TLB entry preservation code.David S. Miller2006-03-203-296/+10
| | | | | | | It is totally unnecessary complexity. After we take over the trap table, we handle all PROM tlb misses fully. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use sparc64_highest_unlocked_tlb_ent in __tsb_context_switch()David S. Miller2006-03-201-6/+8
| | | | | | Instead of ugly hard-coded value. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix bogus flush instruction usage.David S. Miller2006-03-205-17/+30
| | | | | | | | | | Some of the trap code was still assuming that alternate global %g6 was hard coded with current_thread_info(). Let's just consistently flush at KERNBASE when we need a pipeline synchronization. That's locked into the TLB and will always work. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix incorrect TSB lock bit handling.David S. Miller2006-03-201-1/+1
| | | | | | | | | | The TSB_LOCK_BIT define is actually a special value shifted down by 32-bits for the assembler code macros. In C code, this isn't what we want. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill {save,restore}_alternate_globals()David S. Miller2006-03-202-76/+1
| | | | | | | No longer needed now that we no longer have hard-coded alternate global register usage. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Preload TSB entries from update_mmu_cache().David S. Miller2006-03-202-0/+27
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Dynamically grow TSB in response to RSS growth.David S. Miller2006-03-203-10/+176
| | | | | | | | | As the RSS grows, grow the TSB in order to reduce the likelyhood of hash collisions and thus poor hit rates in the TSB. This definitely needs some serious tuning. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add infrastructure for dynamic TSB sizing.David S. Miller2006-03-204-52/+118
| | | | | | | | | | | | | | | This also cleans up tsb_context_switch(). The assembler routine is now __tsb_context_switch() and the former is an inline function that picks out the bits from the mm_struct and passes it into the assembler code as arguments. setup_tsb_parms() computes the locked TLB entry to map the TSB. Later when we support using the physical address quad load instructions of Cheetah+ and later, we'll simply use the physical address for the TSB register value and set the map virtual and PTE both to zero. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: TSB refinements.David S. Miller2006-03-202-0/+39
| | | | | | | | | | Move {init_new,destroy}_context() out of line. Do not put huge pages into the TSB, only base page size translations. There are some clever things we could do here, but for now let's be correct instead of fancy. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Elminate all usage of hard-coded trap globals.David S. Miller2006-03-2013-157/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UltraSPARC has special sets of global registers which are switched to for certain trap types. There is one set for MMU related traps, one set of Interrupt Vector processing, and another set (called the Alternate globals) for all other trap types. For what seems like forever we've hard coded the values in some of these trap registers. Some examples include: 1) Interrupt Vector global %g6 holds current processors interrupt work struct where received interrupts are managed for IRQ handler dispatch. 2) MMU global %g7 holds the base of the page tables of the currently active address space. 3) Alternate global %g6 held the current_thread_info() value. Such hardcoding has resulted in some serious issues in many areas. There are some code sequences where having another register available would help clean up the implementation. Taking traps such as cross-calls from the OBP firmware requires some trick code sequences wherein we have to save away and restore all of the special sets of global registers when we enter/exit OBP. We were also using the IMMU TSB register on SMP to hold the per-cpu area base address, which doesn't work any longer now that we actually use the TSB facility of the cpu. The implementation is pretty straight forward. One tricky bit is getting the current processor ID as that is different on different cpu variants. We use a stub with a fancy calling convention which we patch at boot time. The calling convention is that the stub is branched to and the (PC - 4) to return to is in register %g1. The cpu number is left in %g6. This stub can be invoked by using the __GET_CPUID macro. We use an array of per-cpu trap state to store the current thread and physical address of the current address space's page tables. The TRAP_LOAD_THREAD_REG loads %g6 with the current thread from this table, it uses __GET_CPUID and also clobbers %g1. TRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load the current processor's IRQ software state into %g6. It also uses __GET_CPUID and clobbers %g1. Finally, TRAP_LOAD_PGD_PHYS loads the physical address base of the current address space's page tables into %g7, it clobbers %g1 and uses __GET_CPUID. Many refinements are possible, as well as some tuning, with this stuff in place. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill pgtable quicklists and use SLAB.David S. Miller2006-03-202-21/+15
| | | | | | | | | Taking a nod from the powerpc port. With the per-cpu caching of both the page allocator and SLAB, the pgtable quicklist scheme becomes relatively silly and primitive. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: No need to D-cache color page tables any longer.David S. Miller2006-03-201-65/+6
| | | | | | | Unlike the virtual page tables, the new TSB scheme does not require this ugly hack. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Move away from virtual page tables, part 1.David S. Miller2006-03-2023-831/+489
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We now use the TSB hardware assist features of the UltraSPARC MMUs. SMP is currently knowingly broken, we need to find another place to store the per-cpu base pointers. We hid them away in the TSB base register, and that obviously will not work any more :-) Another known broken case is non-8KB base page size. Also noticed that flush_tlb_all() is not referenced anywhere, only the internal __flush_tlb_all() (local cpu only) is used by the sparc64 port, so we can get rid of flush_tlb_all(). The kernel gets it's own 8KB TSB (swapper_tsb) and each address space gets it's own private 8K TSB. Later we can add code to dynamically increase the size of per-process TSB as the RSS grows. An 8KB TSB is good enough for up to about a 4MB RSS, after which the TSB starts to incur many capacity and conflict misses. We even accumulate OBP translations into the kernel TSB. Another area for refinement is large page size support. We could use a secondary address space TSB to handle those. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: fix sparc_floppy_irq's auxio_register resetingBernhard R Link2006-03-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The patch "[SPARC64]: Get rid of fast IRQ feature" moved the the code from arch/sparc64/kernel/entry.S: lduba [%g7] ASI_PHYS_BYPASS_EC_E, %g5 or %g5, AUXIO_AUX1_FTCNT, %g5 stba %g5, [%g7] ASI_PHYS_BYPASS_EC_E andn %g5, AUXIO_AUX1_FTCNT, %g5 stba %g5, [%g7] ASI_PHYS_BYPASS_EC_E to arch/sparc64/kernel/irq.c: val = readb(auxio_register); val |= AUXIO_AUX1_FTCNT; writeb(val, auxio_register); val &= AUXIO_AUX1_FTCNT; writeb(val, auxio_register); This looks like it it missing a bitwise not, which is reintroduced by this patch. Due to lack of a floppy device, I could not test it, but it looks evident. Signed-off-by: Bernhard R Link <brlink@debian.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Mark __ex_table section correctly.David S. Miller2006-03-0413-14/+14
| | | | | | | | | | We must use the "a" (allocate) attribute every time we emit an entry into the __ex_table section. For consistency, use "a" instead of #alloc which is some Solaris compat cruft GNU as provides on Sparc. Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6Linus Torvalds2006-02-262-9/+21
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| * [SPARC64]: Make cpu_present_map available earlier.David S. Miller2006-02-262-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | The change to kernel/sched.c's init code to use for_each_cpu() requires that the cpu_possible_map be setup much earlier. Set it up via setup_arch(), constrained to NR_CPUS, and later constrain it to max_cpus in smp_prepare_cpus(). This fixes SMP booting on sparc64. Signed-off-by: David S. Miller <davem@davemloft.net>
* | Make Kprobes depend on modulesLinus Torvalds2006-02-261-0/+1
|/ | | | | | | | | Commit 9ec4b1f356b3bad928ae8e2aa9caebfa737d52df made kprobes not compile without module support, so just make that clear in the Kconfig file. Also, since it's marked EXPERIMENTAL, make that dependency explicit too. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [SPARC]: sys_newfstatat --> sys_fstatat64David S. Miller2006-02-122-2/+23
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix sys_newfstatat syscall table entry for 64-bit.Heiko Carstens2006-02-091-1/+1
| | | | | | | | The sparc64 64 bit syscall table seems to be broken as it has compat_sys_newfstatat in its syscall table instead of sys_newfstatat. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Update defconfig.David S. Miller2006-02-071-2/+3
| | | | | | | | Do not enable CONFIG_LOCALVERSION_AUTO by default. When doing kernel development it just leaves a ton of crap around. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC]: Wire up sys_unshare().David S. Miller2006-02-073-32/+4
| | | | | | | | Also, the Solaris syscall table is sized differrently, and does not go beyond entry 255, so trim off the excess entries. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Update defconfig.David S. Miller2006-02-051-8/+13
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add .gitignore file for sparc64 boot images.David S. Miller2006-02-051-0/+4
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill compat_sys_clock_settime sign extension stub.David S. Miller2006-01-302-2/+1
| | | | | | It's wrong and totally unneeded. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC]: Increase NR_SYSCALLS to 299David S. Miller2006-01-221-1/+1
| | | | | | To let new syscalls through. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use compat_sys_futimesat in 32-bit syscall table.David S. Miller2006-01-201-1/+1
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC]: Add support for *at(), ppoll, and pselect syscalls.David S. Miller2006-01-197-261/+95
| | | | | | | | | | This also includes by necessity _TIF_RESTORE_SIGMASK support, which actually resulted in a lot of cleanups. The sparc signal handling code is quite a mess and I should clean it up some day. Signed-off-by: David S. Miller <davem@davemloft.net>
* [PATCH] vfs: *at functions: coreUlrich Drepper2006-01-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Here is a series of patches which introduce in total 13 new system calls which take a file descriptor/filename pair instead of a single file name. These functions, openat etc, have been discussed on numerous occasions. They are needed to implement race-free filesystem traversal, they are necessary to implement a virtual per-thread current working directory (think multi-threaded backup software), etc. We have in glibc today implementations of the interfaces which use the /proc/self/fd magic. But this code is rather expensive. Here are some results (similar to what Jim Meyering posted before). The test creates a deep directory hierarchy on a tmpfs filesystem. Then rm -fr is used to remove all directories. Without syscall support I get this: real 0m31.921s user 0m0.688s sys 0m31.234s With syscall support the results are much better: real 0m20.699s user 0m0.536s sys 0m20.149s The interfaces are for obvious reasons currently not much used. But they'll be used. coreutils (and Jeff's posixutils) are already using them. Furthermore, code like ftw/fts in libc (maybe even glob) will also start using them. I expect a patch to make follow soon. Every program which is walking the filesystem tree will benefit. Signed-off-by: Ulrich Drepper <drepper@redhat.com> Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Al Viro <viro@ftp.linux.org.uk> Acked-by: Ingo Molnar <mingo@elte.hu> Cc: Michael Kerrisk <mtk-manpages@gmx.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6Linus Torvalds2006-01-184-6/+32
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| * [SPARC64]: Fix build with CONFIG_COMPAT disabled.David S. Miller2006-01-181-0/+4
| | | | | | | | | | | | Based upon a report and preliminary patch from Jim Gifford. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Serial Console for E250 PatchEddie C. Dost2006-01-182-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | From: Eddie C. Dost <ecd@brainaid.de> I have the following patch for serial console over the RSC (remote system controller) on my E250 machine. It basically adds support for input-device=rsc and output-device=rsc from OBP, and allows 115200,8,n,1,- serial mode setting. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Update defconfig.David S. Miller2006-01-181-6/+18
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* | [PATCH] e1000: Added disable packet split capabilityJesse Brandeburg2006-01-181-0/+1
|/ | | | | | | | | Adds the ability to disability packet split at compile time and use the legacy receive path on PCI express hardware. Made this a CONFIG option and modified the Kconfig, to reflect the new option. Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: John Ronciak <john.ronciak@intel.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
* [SPARC64]: Eliminate race condition reading Hummingbird STICK registerRichard Mortimer2006-01-171-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure a consistent value is read from the STICK register by ensuring that both high and low are read without high changing due to a roll over of the low register. Various Debian/SPARC users (myself include) have noticed problems with Hummingbird based systems. The symptoms are that the system time is seen to jump forward 3 days, 6 hours, 11 minutes give or take a few seconds. In many cases the system then hangs some time afterwards. I've spotted a race condition in the code to read the STICK register. I could not work out why 3d, 6h, 11m is important but guess that it is due to the 2^32 jump of STICK (forwards on one read and then the next read will seem to be backwards) during a timer interrupt. I'm guessing that a change of -2^32 will get converted to a large unsigned increment after the arithmetic manipulation between STICK, nanoseconds, jiffies etc. I did a test where I modified __hbird_read_stick to artificially inject rollover faults forcefully every few seconds. With this I saw the clock jump over 6 times in 12 hours compared to once every month or so. Signed-off-by: Richard Mortimer <richm@oldelvet.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
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