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path: root/arch/sh/drivers/pci/ops-sh7785lcr.c
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* sh: pci: Consolidate SH7780 PCIC IRQ routing.Paul Mundt2009-04-171-27/+0
| | | | | | | | Now that the platform code is a bit leaner, we can start consolidating the various IRQ routing implementations. There are effectively only 2 variants, and the others can use those directly. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pci: Kill off platform-specific multi-window mappings.Paul Mundt2009-04-171-17/+0
| | | | | | | | | | | Commit 68b42d1b548be1840aff7122fdebeb804daf0fa3 ("sh: sh7785lcr: Map whole PCI address space.") changed around the semantics of how various chip-selects are made accessible to PCI. Now that there is a single large mapping covering from CS0-CS6, there is no longer any need to do multi-window mapping. Subsequently, all of the differing implementations can be consolidated in to pci-sh7780. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pci: Consolidate PCI I/O and mem window definitions for SH7780.Paul Mundt2009-04-171-20/+1
| | | | | | | | This consolidates all of the PCI I/O and memory window definitions across the pci-sh7780 users in pci-sh7780 itself. No functional changes, in that every platform had exactly the same implementation. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pci: Kill off unused SH4_PCIC_NO_RESET code.Paul Mundt2009-04-161-2/+0
| | | | | | Nothing ended up using this anymore, so just kill it off. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: sh7785lcr: Update for recent PCI changes.Paul Mundt2009-04-161-2/+2
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: drop duplicate symbol export on dreamcast and sh7785lcr.Paul Mundt2009-04-161-1/+0
| | | | | | | With board_pci_channels now being exported in a single place, update the boards that duplicated the export. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: sh7785lcr: fix PCI address map for 32-bit modeYoshihiro Shimoda2009-04-061-0/+5
| | | | | | | | | | | Fix the problem that cannot work PCI device on 32-bit mode because influence of the commit 68b42d1b548be1840aff7122fdebeb804daf0fa3 ("sh: sh7785lcr: Map whole PCI address space."). So this patch was implement like a 29-bit mode, map whole physical address space of DDR-SDRAM. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: sh7785lcr: Map whole PCI address space.Takashi Yoshii2009-04-041-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | PCI still doesn't work on sh7785lcr 29bit 256M map mode. On SH7785, PCI -> SHwy address translation is not base+offset but somewhat like base|offset (See HW Manual (rej09b0261) Fig. 13.11). So, you can't export CS2,3,4,5 by 256M at CS2 (results CS0,1,2,3 exported, I guess). There are two candidates. a) 128M@CS2 + 128M@CS4 b) 512M@CS0 Attached patch is B. It maps 512M Byte at 0 independently of memory size. It results CS0 to CS6 and perhaps some more being accessible from PCI. Tested on 7785lcr 29bit 128M map 7785lcr 29bit 256M map (NOT tested on 32bit) Signed-off-by: Takashi YOSHII <yoshii.takashi@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Renesas R0P7785LC0011RL board supportYoshihiro Shimoda2008-07-281-0/+66
This adds initial support for the Renesas R0P7785LC0011RL board. This patch supports 29bit address mode only. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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