summaryrefslogtreecommitdiffstats
path: root/arch/riscv/kernel
Commit message (Expand)AuthorAgeFilesLines
* Merge tag 'riscv-for-linus-4.16-merge_window' of git://git.kernel.org/pub/scm...Linus Torvalds2018-02-077-42/+193
|\
| * riscv: rename sptbr to satpChristoph Hellwig2018-01-301-3/+3
| * riscv: add ZONE_DMA32Christoph Hellwig2018-01-301-0/+9
| * riscv: disable SUM in the exception handlerChristoph Hellwig2018-01-301-3/+6
| * riscv: remove redundant unlikely()Tobias Klauser2018-01-301-1/+1
| * riscv/ftrace: Add basic supportAlan Kao2018-01-303-0/+174
| * RISC-V: Remove mem_end command line processingPalmer Dabbelt2018-01-301-19/+0
| * RISC-V: Remove duplicate command-line parsing logicMichael Clark2018-01-301-16/+0
* | Merge branch 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2018-01-311-1/+1
|\ \ | |/ |/|
| * riscv: use linux/uaccess.h, not asm/uaccess.h...Al Viro2017-12-041-1/+1
* | riscv: rename SR_* constants to match the specChristoph Hellwig2018-01-072-6/+6
* | RISC-V: Make __NR_riscv_flush_icache visible to userspacePalmer Dabbelt2018-01-072-2/+0
* | RISC-V: Remove unused CONFIG_HVC_RISCV_SBI codePalmer Dabbelt2017-12-111-11/+0
* | RISC-V: Logical vs Bitwise typoDan Carpenter2017-12-111-1/+1
* | RISC-V: Fixes for clean allmodconfig buildPalmer Dabbelt2017-12-014-3/+15
|\ \
| * | RISC-V: Provide stub of setup_profiling_timer()Olof Johansson2017-11-301-0/+7
| * | RISC-V: Export some expected symbols for modulesOlof Johansson2017-11-302-0/+5
| * | RISC-V: move empty_zero_page definition to C and export itOlof Johansson2017-11-302-3/+3
| |/
* | RISC-V: Clean up an unused includePalmer Dabbelt2017-11-301-1/+0
* | RISC-V: Allow userspace to flush the instruction cacheAndrew Waterman2017-11-305-0/+67
* | RISC-V: Flush I$ when making a dirty page executableAndrew Waterman2017-11-301-0/+48
* | RISC-V: Add VDSO entries for clock_get/gettimeofday/getcpuAndrew Waterman2017-11-276-1/+113
* | RISC-V: Remove __vdso_cmpxchg{32,64} symbol versionsPalmer Dabbelt2017-11-271-2/+0
|/
* RISC-V: Build InfrastructurePalmer Dabbelt2017-09-263-0/+126
* RISC-V: User-facing APIPalmer Dabbelt2017-09-2612-0/+977
* RISC-V: Task implementationPalmer Dabbelt2017-09-263-0/+915
* RISC-V: Generic library routines and assemblyPalmer Dabbelt2017-09-261-0/+177
* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-2611-0/+1292
OpenPOWER on IntegriCloud