summaryrefslogtreecommitdiffstats
path: root/arch/riscv/kernel/setup.c
Commit message (Collapse)AuthorAgeFilesLines
* RISC-V: SMP cleanup and new featuresPalmer Dabbelt2018-10-221-0/+10
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch series now has evolved to contain several related changes. 1. Updated the assorted cleanup series by Palmer. The original cleanup patch series can be found here. http://lists.infradead.org/pipermail/linux-riscv/2018-August/001232.html 2. Implemented decoupling linux logical CPU ids from hart id. Some of the work has been inspired from ARM64. Tested on QEMU & HighFive Unleashed board with/without SMP enabled. 3. Included Anup's cleanup and IPI stat patch. All the patch series have been combined to avoid conflicts as a lot of common code is changed different patch sets. Atish has mostly addressed review comments and fixed checkpatch errors from Palmer's and Anup's series. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | Setup the cpu_logical_map during boot. Moreover, every SBI call and PLIC context are based on the physical hartid. Use the logical CPU to hartid mapping to pass correct hartid to respective functions. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * RISC-V: Add logical CPU indexing for RISC-VAtish Patra2018-10-221-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, both Linux CPU id and hart id are same. This is not recommended as it will lead to discontinuous CPU indexing in Linux. Moreover, kdump kernel will run from CPU0 which would be absent if we follow existing scheme. Implement a logical mapping between Linux CPU id and hart id to decouple these two. Always mark the boot processor as CPU0 and all other CPUs get the logical CPU id based on their booting order. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* | RISC-V: Use swiotlb on RV64 onlyZong Li2018-10-221-0/+3
|/ | | | | | | | Only RV64 supports swiotlb. On RV32, it don't select the SWIOTLB. Signed-off-by: Zong Li <zong@andestech.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISCV: Fix end PFN for low memoryAtish Patra2018-10-021-1/+1
| | | | | | | | | | | | | Use memblock_end_of_DRAM which provides correct last low memory PFN. Without that, DMA32 region becomes empty resulting in zero pages being allocated for DMA32. This patch is based on earlier patch from palmer which never merged into 4.19. I just edited the commit text to make more sense. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* riscv: Do not overwrite initrd_start and initrd_endGuenter Roeck2018-09-041-7/+0
| | | | | | | | | | | | | setup_initrd() overwrites initrd_start and initrd_end if __initramfs_size is larger than 0, which is always true even if there is no embedded initramfs. This prevents booting qemu with "-initrd" parameter. Overwriting initrd_start and initrd_end is not necessary since __initramfs_start and __initramfs_size are used directly in populate_rootfs() to load the built-in initramfs, so just drop that code. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Add early printk support via the SBI consolePalmer Dabbelt2018-08-131-0/+27
| | | | | | | | | | This code lives entirely within the RISC-V arch code. I've left it within an "#ifdef CONFIG_EARLY_PRINTK" despite always having EARLY_PRINTK support on RISC-V just in case someone wants to remove it. Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* riscv: remove unnecessary of_platform_populate callRob Herring2018-07-041-5/+0
| | | | | | | | | | | | | The DT core will call of_platform_default_populate, so it is not necessary for arch specific code to call it unless there are custom match entries, auxdata or parent device. Neither of those apply here, so remove the call. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: linux-riscv@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* riscv: add swiotlb supportChristoph Hellwig2018-05-191-0/+2
| | | | | | | | | | | | | | | | | | All RISC-V platforms today lack an IOMMU. However, legacy PCI devices sometimes require DMA-memory to be in the low 32 bits. To make this work, we enable the software-based bounce buffers from swiotlb. They only impose overhead when the device in question cannot address the full 64-bit address space, so a perfect fit. This patch assumes that DMA is coherent with the processor and the PCI bus. It also assumes that the processor and devices share a common address space. This is true for all RISC-V platforms so far. [changelog stolen from an earlier patch by Palmer Dabbelt that did the more complicated swiotlb wireup before the recent consolidation] Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
* Rename sbi_save to parse_dtb to improve code readabilityMichael Clark2018-02-201-1/+1
| | | | | | | | The sbi_ prefix would seem to indicate an SBI interface, and save is not very specific. After applying this patch, reading head.S makes more sense. Signed-off-by: Michael Clark <michaeljclark@mac.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* riscv: add ZONE_DMA32Christoph Hellwig2018-01-301-0/+9
| | | | | | | | | | | | | This patch allows devices that require memory that can be addressed using 32-bit addresses to work easily on RISC-V systems. The newly improved dma-direct ops will tap into this pool automatically for 32-bit addressing. Based on an earlier patch from Wesley W. Terpstra. CC: Wesley W. Terpstra <terpstra@sifive.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Remove mem_end command line processingPalmer Dabbelt2018-01-301-19/+0
| | | | | | | | | This is just some cruft left over from before the port converted to device tree. The right way to handle memory regions is to specify them in the device tree, which BBL (our simplest bootloader) is already capable of doing. This patch simply removes the cruft. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Remove duplicate command-line parsing logicMichael Clark2018-01-301-16/+0
| | | | | | | | | | | | | | | | | | builtin_cmdline handling is present in drivers/of/fdt.c so the duplicate logic in arch/riscv/setup.c results in duplication of the builtin command line. e.g. CONFIG_CMDLINE="root=/dev/vda ro" gets appended twice and gives "root=/dev/vda ro root=/dev/vda ro" Before this patch: [ 0.000000] Kernel command line: root=/dev/vda ro root=/dev/vda ro After this patch: [ 0.000000] Kernel command line: root=/dev/vda ro Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Remove unused CONFIG_HVC_RISCV_SBI codePalmer Dabbelt2017-12-111-11/+0
| | | | | | | | | | | | This is code that probably should never have made it into the kernel in the first place: it depends on a driver that hadn't been reviewed yet. During the HVC_SBI_RISCV review process a better way of doing this was suggested, but that means this code is defunct. It's compile-time disabled in 4.15 because the driver isn't in, so I think it's safe to just remove this for now. CC: Greg KH <gregkh@linuxfoundation.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Export some expected symbols for modulesOlof Johansson2017-11-301-0/+2
| | | | | | | | | These are the ones needed by current allmodconfig, so add them instead of everything other architectures are exporting -- the rest can be added on demand later if needed. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: move empty_zero_page definition to C and export itOlof Johansson2017-11-301-0/+3
| | | | | | | Needed by some modules (exported by other architectures). Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-261-0/+257
This contains the various __init C functions, the initial assembly kernel entry point, and the code to reset the system. When a file was init-related this patch contains the entire file. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
OpenPOWER on IntegriCloud