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* powerpc: Move the testing of CPU_FTR_COHERENT_ICACHE into __flush_icache_rangeKevin Hao2013-08-143-3/+5
| | | | | | | | | | | | | | | In function flush_icache_range(), we use cpu_has_feature() to test the feature bit of CPU_FTR_COHERENT_ICACHE. But this seems not optimal for two reasons: a) For ppc32, the function __flush_icache_range() already do this check with the macro END_FTR_SECTION_IFSET. b) Compare with the cpu_has_feature(), the method of using macro END_FTR_SECTION_IFSET will not introduce any runtime overhead. [And while at it, add the missing required isync] -- BenH Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Stop using non-architected shared_proc field in lppacaAnton Blanchard2013-08-147-12/+23
| | | | | | | | | | | | | Although the shared_proc field in the lppaca works today, it is not architected. A shared processor partition will always have a non zero yield_count so use that instead. Create a wrapper so users don't have to know about the details. In order for older kernels to continue to work on KVM we need to set the shared_proc bit. While here, remove the ugly bitfield. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/pci: Don't use bitfield for force_32bit_msiAnton Blanchard2013-08-142-2/+2
| | | | | | | Fix a sparse warning about force_32bit_msi being a one bit bitfield. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Fix a number of sparse warningsAnton Blanchard2013-08-1413-20/+20
| | | | | | | Address some of the trivial sparse warnings in arch/powerpc. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/pseries: Simplify H_GET_TERM_CHARAnton Blanchard2013-08-142-27/+9
| | | | | | | | | plpar_get_term_char is only used once and just adds a layer of complexity to H_GET_TERM_CHAR. plpar_put_term_char isn't used at all so we can remove it. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Simplify logic in include/uapi/asm/elf.hAnton Blanchard2013-08-141-12/+7
| | | | | | | | Simplify things by putting all the 32bit and 64bit defines together instead of in two spots. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Remove SAVE_VSRU and REST_VSRU macrosAnton Blanchard2013-08-141-13/+0
| | | | | | | | We always use VMX loads and stores to manage the high 32 VSRs. Remove these unused macros. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Wrap MSR macros with parenthesesAnton Blanchard2013-08-142-8/+8
| | | | | | | Not having parentheses around a macro is asking for trouble. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Handle unaligned ldbrx/stdbrxAnton Blanchard2013-08-141-0/+10
| | | | | | | | | | | | | | | | | | | | | Normally when we haven't implemented an alignment handler for a load or store instruction the process will be terminated. The alignment handler uses the DSISR (or a pseudo one) to locate the right handler. Unfortunately ldbrx and stdbrx overlap lfs and stfs so we incorrectly think ldbrx is an lfs and stdbrx is an stfs. This bug is particularly nasty - instead of terminating the process we apply an incorrect fixup and continue on. With more and more overlapping instructions we should stop creating a pseudo DSISR and index using the instruction directly, but for now add a special case to catch ldbrx/stdbrx. Signed-off-by: Anton Blanchard <anton@samba.org> Cc: <stable@vger.kernel.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Align p_tocAnton Blanchard2013-08-141-0/+1
| | | | | | | | | p_toc is an 8 byte relative offset to the TOC that we place in the text section. This means it is only 4 byte aligned where it should be 8 byte aligned. Add an explicit alignment. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Merge remote-tracking branch 'scott/next' into nextBenjamin Herrenschmidt2013-08-0937-143/+1047
|\ | | | | | | Merge some Freescale updates from Scott Wood
| * powerpc/e500: Update compilation flags with core specific optionsCatalin Udma2013-08-071-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_E500 is enabled, the compilation flags are updated specifying the target core -mcpu=e5500/e500mc/8540 Also remove -Wa,-me500, being incompatible with -mcpu=e5500/e6500 The assembler option is redundant if the -mcpu= flag is set. The patch fixes the kernel compilation problem for e5500/e6500 when using gcc option -mcpu=e5500/e6500. Signed-off-by: Catalin Udma <catalin.udma@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl: Enable CONFIG_DEVTMPFS_MOUNT so /dev can be mounted correctlyZhenhua Luo2013-08-076-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using recent udev, the /dev node mount requires CONFIG_DEVTMPFS_MOUNT is enabled in Kernel. The patch enables the option in defconfig of Freescale QorIQ targets. Changed defconfig list: arch/powerpc/configs/85xx/p1023rds_defconfig arch/powerpc/configs/corenet32_smp_defconfig arch/powerpc/configs/corenet64_smp_defconfig arch/powerpc/configs/mpc85xx_smp_defconfig arch/powerpc/configs/mpc85xx_defconfig arch/powerpc/configs/mpc83xx_defconfig Signed-off-by: Zhenhua Luo <zhenhua.luo@freescale.com> [scottwood@freescale.com: added mpc83xx and non-smp mpc85xx] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/pci: fix PCI-e check link issueYuanquan Chen2013-08-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Freescale powerpc platform, the PCI-e bus number uses the reassign mode by default. It means the second PCI-e controller's hose->first_busno is the first controller's last bus number adding 1. For some hotpluged device(or controlled by FPGA), the device is linked to PCI-e slot at linux runtime. It needs rescan for the system to add it and driver it to work. It successes to rescan the device linked to the first PCI-e controller's slot, but fails to rescan the device linked to the second PCI-e controller's slot. The cause is that the bus->number is reset to 0, which isn't equal to the hose->first_busno for the second controller checking PCI-e link. So it doesn't really check the PCI-e link status, the link status is always no_link. The device won't be really rescaned. Reset the bus->number to hose->first_busno in the function fsl_pcie_check_link(), it will do the real checking PCI-e link status for the second controller, the device will be rescaned. Signed-off-by: Yuanquan Chen <Yuanquan.Chen@freescale.com> Tested-by: Rojhalat Ibrahim <imr@rtschenk.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl-pci: enable SWIOTLB in function setup_pci_atmuKevin Hao2013-08-071-19/+3
| | | | | | | | | | | | | | | | | | This function contains all the stuff we need to check if SWIOTLB should be enabled or not. So it is more convenient to enable the SWIOTLB here than later. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl-pci: fix the unreachable warning messageKevin Hao2013-08-071-1/+1
| | | | | | | | | | | | | | The (1ull << mem_log) is never greater than mem unless mem_log++; Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/mpc85xx: remove the unneeded pci init functions for corenet ds boardKevin Hao2013-08-071-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | The function pci_devs_phb_init is invoked more earlier than we really probe the pci controller, so it does nothing at all. And we also don't need the pci_dn stuff for the fsl powerpc64 boards, just remove it. It also seems that we don't support ISA on all the current corenet ds boards. So picking a primary bus seems useless, remove that function too. Signed-off-by: Kevin Hao <haokexin@gmail.com>
| * powerpc/85xx: add the P1020RDB-PD DTS supportHaijun.Zhang2013-08-071-0/+280
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Overview of P1020RDB-PD device: - DDR3 2GB - NOR flash 64MB - NAND flash 128MB - SPI flash 16MB - I2C EEPROM 256Kb - eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch - eTSEC2 (SGMII PHY) - eTSEC3 (RGMII PHY) - SDHC - 1 USB ports - TDM ports - PCIe Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Xie Xiaobo-R63061 <X.Xie@freescale.com> CC: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/85xx: add P1020RDB-PD platform supportHaijun.Zhang2013-08-071-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The p1020rdb-pd has the similar feature as the p1020rdb. Therefore, p1020rdb-pd use the same platform file as the p1/p2 rdb board. Overview of P1020RDB-PD platform: - DDR3 2GB - NOR flash 64MB - NAND flash 128MB - SPI flash 16MB - I2C EEPROM 256Kb - eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch - eTSEC2 (SGMII PHY) - eTSEC3 (RGMII PHY) - SDHC - 2 USB ports - 4 TDM ports - PCIe Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> CC: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/85xx: Move ePAPR paravirt initialization earlierLaurentiu TUDOR2013-08-074-13/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | At console init, when the kernel tries to flush the log buffer the ePAPR byte-channel based console write fails silently, losing the buffered messages. This happens because The ePAPR para-virtualization init isn't done early enough so that the hcall instruction to be set, causing the byte-channel write hcall to be a nop. To fix, change the ePAPR para-virt init to use early device tree functions and move it in early init. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl_msi: add MSIIR1 support for MPIC v4.3Minghuan Lian2013-08-072-41/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original MPIC MSI bank contains 8 registers, MPIC v4.3 MSI bank contains 16 registers, and this patch adds NR_MSI_REG_MAX and NR_MSI_IRQS_MAX to describe the maximum capability of MSI bank. MPIC v4.3 provides MSIIR1 to index these 16 MSI registers. MSIIR1 uses different bits definition than MSIIR. This patch adds ibs_shift and srs_shift to indicate the bits definition of the MSIIR and MSIIR1, so the same code can handle the MSIIR and MSIIR1 simultaneously. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> [scottwood@freescale.com: reinstated static on all_avail] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/dts: add MPIC v4.3 dts nodeMinghuan Lian2013-08-073-2/+151
| | | | | | | | | | | | | | | | | | | | | | For the latest platform T4 and B4, MPIC controller has been updated to v4.3. This patch adds a new file to describe the latest MPIC. The MSI blocks number is increased to four, the registers number of each block is increased to sixteen. MSIIR1 has been added to access these sixteen MSI registers. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/msi: Fix compile error on mpc83xxHongtao Jia2013-08-071-0/+7
| | | | | | | | | | | | | | | | | | | | | | mpic_get_primary_version() is not defined when not using MPIC. The compile error log like: arch/powerpc/sysdev/built-in.o: In function `fsl_of_msi_probe': fsl_msi.c:(.text+0x150c): undefined reference to `fsl_mpic_primary_get_version' Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/perf: Add e6500 PMU driverPriyanka Jain2013-08-073-2/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | e6500 core performance monitors has the following features: - 6 performance monitor counters - 512 events supported - no threshold events e6500 PMU has more specific events (Data L1 cache misses, Instruction L1 cache misses, etc ) than e500 PMU (which only had Data L1 cache reloads, etc). Where available, the more specific events have been used which will produce slightly different results than e500 PMU equivalents. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/perf: add 2 additional performance monitor counters for e6500 coreLijun Pan2013-08-074-1/+67
| | | | | | | | | | | | | | There are 6 counters in e6500 core instead of 4 in e500 core. Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/perf: increase the perf HW events to 6Catalin Udma2013-08-072-1/+7
| | | | | | | | | | | | | | | | | | | | | | This change is required after the e6500 perf support has been added. There are 6 counters in e6500 core instead of 4 in e500 core and the MAX_HWEVENTS counter should be changed accordingly from 4 to 6. Added also runtime check for counters overflow. Signed-off-by: Catalin Udma <catalin.udma@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/perf: correct typos in counter enumerationLijun Pan2013-08-071-4/+4
| | | | | | | | | | Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl-booke: Rename b4qds.dts -> b4qds.dtsi.Ian Campbell2013-08-073-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file is a common include for B4860 and B4420 but is not a valid DTS itself: DTC arch/powerpc/boot/b4qds.dtb Error: arch/powerpc/boot/dts/b4qds.dts:35.1-2 syntax error FATAL ERROR: Unable to parse input tree make[1]: *** [arch/powerpc/boot/b4qds.dtb] Error 1 make: *** [b4qds.dtb] Error 2 I spotted in build tests of device-tree.git, announcement https://lkml.org/lkml/2013/4/24/209, which builds *.dts. Probably no one would do this this in real life on linux.git but it still seems worth fixing. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Cc: Shaveta Leekha <shaveta@freescale.com> Cc: Minghuan Lian <Minghuan.Lian@freescale.com> Cc: Andy Fleming <afleming@freescale.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Ramneek Mehresh <ramneek.mehresh@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/mpc85xx: invalidate TLB after hibernation resumeDongsheng Wang2013-07-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This problem belongs to the core synchronization issues. The cpu1 already updated spin_table values, but bootcore cannot get this value in time. After bootcpu hibiernation restore the pages. we are now running with the kernel data of the old kernel fully restored. if we reset the non-bootcpus that will be reset cache(tlb), the non-bootcpus will get new address(map virtual and physical address spaces). but bootcpu tlb cache still use boot kernel data, so we need to invalidate the bootcpu tlb cache make it to get new main memory data. log: Enabling non-boot CPUs ... smp_85xx_kick_cpu: timeout waiting for core 1 to reset smp: failed starting cpu 1 (rc -2) Error taking CPU1 up: -2 Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: Anton Vorontsov <anton@enomsg.org> [scottwood@freescale.com: reworded code comment for clarity] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl_msi: fix error return code in fsl_of_msi_probe()Wei Yongjun2013-07-301-3/+2
| | | | | | | | | | | | | | | | Fix to return a negative error code in the MSI bitmap alloc error handling case instead of 0, as done elsewhere in this function. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xxHongtao Jia2013-07-304-1/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe goes down. when the link goes down, Non-posted transactions issued via the ATMU requiring completion result in an instruction stall. At the same time a machine-check exception is generated to the core to allow further processing by the handler. We implements the handler which skips the instruction caused the stall. This patch depends on patch: powerpc/85xx: Add platform_device declaration to fsl_pci.h Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Liu Shuo <soniccat.liu@gmail.com> Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc: Move opcode definitions from kvm/emulate.c to asm/ppc-opcode.hHongtao Jia2013-07-302-44/+48
| | | | | | | | | | | | | | | | | | | | | | | | Opcode and xopcode are useful definitions not just for KVM. Move these definitions to asm/ppc-opcode.h for public use. Also add the opcodes for LHAUX and LWZUX. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> [scottwood@freesacle.com: update commit message and rebase] Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Merge branch 'merge' of ↵Linus Torvalds2013-08-028-25/+73
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc Pull powerpc fixes from Ben Herrenschmidt: "Here is not quite a handful of powerpc fixes for rc3. The windfarm fix is a regression fix (though not a new one), the PMU interrupt rename is not a fix per-se but has been submitted a long time ago and I kept forgetting to put it in (it puts us back in sync with x86), the other perf bit is just about putting an API/ABI bit definition in the right place for userspace to consume, and finally, we have a fix for the VPHN (Virtual Partition Home Node) feature (notification that the hypervisor is moving nodes around) which could cause lockups so we may as well fix it now" * 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc/windfarm: Fix noisy slots-fan on Xserve (rm31) powerpc: VPHN topology change updates all siblings powerpc/perf: Export PERF_EVENT_CONFIG_EBB_SHIFT to userspace powerpc: Rename PMU interrupts from CNT to PMI
| * | powerpc: VPHN topology change updates all siblingsRobert Jennings2013-08-012-15/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an associativity level change is found for one thread, the siblings threads need to be updated as well. This is done today for PRRN in stage_topology_update() but is missing for VPHN in update_cpu_associativity_changes_mask(). This patch will correctly update all thread siblings during a topology change. Without this patch a topology update can result in a CPU in init_sched_groups_power() getting stuck indefinitely in a loop. This loop is built in build_sched_groups(). As a result of the thread moving to a node separate from its siblings the struct sched_group will have its next pointer set to point to itself rather than the sched_group struct of the next thread. This happens because we have a domain without the SD_OVERLAP flag, which is correct, and a topology that doesn't conform with reality (threads on the same core assigned to different numa nodes). When this list is traversed by init_sched_groups_power() it will reach the thread's sched_group structure and loop indefinitely; the cpu will be stuck at this point. The bug was exposed when VPHN was enabled in commit b7abef0 (v3.9). Cc: <stable@vger.kernel.org> [v3.9+] Reported-by: Jan Stancek <jstancek@redhat.com> Signed-off-by: Robert Jennings <rcj@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/perf: Export PERF_EVENT_CONFIG_EBB_SHIFT to userspaceMichael Ellerman2013-08-015-9/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | We use bit 63 of the event code for userspace to request that the event be counted using EBB (Event Based Branches). Export this value, making it part of the API - though only on processors that support EBB. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc: Rename PMU interrupts from CNT to PMIMichael Ellerman2013-08-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Back in commit 89713ed "Add timer, performance monitor and machine check counts to /proc/interrupts" we added a count of PMU interrupts to the output of /proc/interrupts. At the time we named them "CNT" to match x86. However in commit 89ccf46 "Rename 'performance counter interrupt'", the x86 guys renamed theirs from "CNT" to "PMI". Arguably changing the name could break someone's script, but I think the chance of that is minimal, and it's preferable to have a name that 1) is somewhat meaningful, and 2) matches x86. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | | Merge tag 'pci-v3.11-fixes-1' of ↵Linus Torvalds2013-08-023-3/+3
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: "Yinghai fixed a couple regressions: one resource assignment problem introduced in v3.10 that showed up with SR-IOV on powerpc, and another SR-IOV hot-remove issue related to refcounting changes we merged for v3.11. Yinghai is still working on another SR-IOV-related fix or two, which will be simpler if pciehp is non-modular, so I included the Kconfig changes now to get them in earlier. Finally, a minor fix for the ARM Marvell EBU host bridge driver that was merged for v3.11 Hotplug: PCI: pciehp: Fix null pointer deref when hot-removing SR-IOV device PCI: hotplug: Convert to be builtin only, not modular PCI: pciehp: Convert pciehp to be builtin only, not modular Resource allocation: PCI: Retry allocation of only the resource type that failed ARM: PCI: mvebu: Disable prefetchable memory support in PCI-to-PCI bridge" * tag 'pci-v3.11-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: mvebu: Disable prefetchable memory support in PCI-to-PCI bridge PCI: Retry allocation of only the resource type that failed PCI: pciehp: Convert pciehp to be builtin only, not modular PCI: hotplug: Convert to be builtin only, not modular PCI: pciehp: Fix null pointer deref when hot-removing SR-IOV device
| * | PCI: hotplug: Convert to be builtin only, not modularBjorn Helgaas2013-07-253-3/+3
| |/ | | | | | | | | | | | | | | Convert CONFIG_HOTPLUG_PCI from tristate to bool. This only affects the hotplug core; several of the hotplug drivers can still be modules. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Yinghai Lu <yinghai@kernel.org>
* | powerpc/perf: BHRB filter configuration should follow the taskAnshuman Khandual2013-07-241-1/+4
| | | | | | | | | | | | | | | | | | | | | | When the task moves around the system, the corresponding cpuhw per cpu strcuture should be popullated with the BHRB filter request value so that PMU could be configured appropriately with that during the next call into power_pmu_enable(). Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/perf: Ignore separate BHRB privilege state filter requestAnshuman Khandual2013-07-241-9/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Completely ignore BHRB privilege state filter request as we are already configuring that with privilege state filtering attribute for the accompanying PMU event. This would help achieve cleaner user space interaction for BHRB. This patch fixes a situation like this Before patch:- ------------ ./perf record -j any -e branch-misses:k ls Error: The sys_perf_event_open() syscall returned with 95 (Operation not supported) for event (branch-misses:k). /bin/dmesg may provide additional information. No CONFIG_PERF_EVENTS=y kernel support configured? Here 'perf record' actually copies over ':k' filter request into BHRB privilege state filter config and our previous check in kernel would fail that. After patch:- ------------- ./perf record -j any -e branch-misses:k ls perf perf.data perf.data.old test-mmap-ring [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.002 MB perf.data (~102 samples)] Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/powernv: Mark pnv_pci_init_ioda2_phb() as __initBjorn Helgaas2013-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mark pnv_pci_init_ioda2_phb() as __init. It is called only from an init function (pnv_pci_init()), and it calls an init function (pnv_pci_init_ioda_phb()): pnv_pci_init # init pnv_pci_init_ioda2_phb # non-init pnv_pci_init_ioda_phb # init This should fix a section mismatch warning. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/mm: Use the correct SLB(LLP) encoding in tlbie instructionAneesh Kumar K.V2013-07-241-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | The sllp value is stored in mmu_psize_defs in such a way that we can easily OR the value to get the operand for slbmte instruction. ie, the L and LP bits are not contiguous. Decode the bits and use them correctly in tlbie. regression is introduced by 1f6aaaccb1b3af8613fe45781c1aefee2ae8c6b3 "powerpc: Update tlbie/tlbiel as per ISA doc" Reported-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/mm: Fix fallthrough bug in hpte_decodeAneesh Kumar K.V2013-07-241-0/+2
| | | | | | | | | | | | | | | | | | | | We should not fallthrough different case statements in hpte_decode. Add break statement to break out of the switch. The regression is introduced by dcda287a9b26309ae43a091d0ecde16f8f61b4c0 "powerpc/mm: Simplify hpte_decode" Reported-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/pseries: Fix a typo in pSeries_lpar_hpte_insert()Denis Kirjanov2013-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Commit 801eb73f45371accc78ca9d6d22d647eeb722c11 introduced a bug while checking PTE flags. We have to drop the _PAGE_COHERENT flag when __PAGE_NO_CACHE is set and the cache update policy is not write-through (i.e. _PAGE_WRITETHRU is not set) Signed-off-by: Denis Kirjanov <kda@linux-powerpc.org> Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> CC: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/eeh: Introdce flag to protect sysfsGavin Shan2013-07-245-4/+22
| | | | | | | | | | | | | | | | | | The patch introduces flag EEH_DEV_SYSFS to keep track that the sysfs entries for the corresponding EEH device (then PCI device) has been added or removed, in order to avoid race condition. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/eeh: Fix unbalanced enable for IRQGavin Shan2013-07-241-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch fixes following issue: Unbalanced enable for IRQ 23 ------------[ cut here ]------------ WARNING: at kernel/irq/manage.c:437 : NIP [c00000000016de8c] .__enable_irq+0x11c/0x140 LR [c00000000016de88] .__enable_irq+0x118/0x140 Call Trace: [c000003ea1f23880] [c00000000016de88] .__enable_irq+0x118/0x140 (unreliable) [c000003ea1f23910] [c00000000016df08] .enable_irq+0x58/0xa0 [c000003ea1f239a0] [c0000000000388b4] .eeh_enable_irq+0xc4/0xe0 [c000003ea1f23a30] [c000000000038a28] .eeh_report_reset+0x78/0x130 [c000003ea1f23ac0] [c000000000037508] .eeh_pe_dev_traverse+0x98/0x170 [c000003ea1f23b60] [c0000000000391ac] .eeh_handle_normal_event+0x2fc/0x3d0 [c000003ea1f23bf0] [c000000000039538] .eeh_handle_event+0x2b8/0x2c0 [c000003ea1f23c90] [c000000000039600] .eeh_event_handler+0xc0/0x170 [c000003ea1f23d30] [c0000000000da9a0] .kthread+0xf0/0x100 [c000003ea1f23e30] [c00000000000a1dc] .ret_from_kernel_thread+0x5c/0x80 Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/eeh: Don't use pci_dev during BAR restoreGavin Shan2013-07-244-16/+91
| | | | | | | | | | | | | | | | | | | | | | | | While restoring BARs for one specific PCI device, the pci_dev instance should have been released. So it's not reliable to use the pci_dev instance on restoring BARs. However, we still need some information (e.g. PCIe capability position, header type) from the pci_dev instance. So we have to store those information to EEH device in advance. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/eeh: Use partial hotplug for EEH unaware driversGavin Shan2013-07-247-24/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When EEH error happens to one specific PE, some devices with drivers supporting EEH won't except hotplug on the device. However, there might have other deivces without driver, or with driver without EEH support. For the case, we need do partial hotplug in order to make sure that the PE becomes absolutely quite during reset. Otherise, the PE reset might fail and leads to failure of error recovery. The current code doesn't handle that 'mixed' case properly, it either uses the error callbacks to the drivers, or tries hotplug, but doesn't handle a PE (EEH domain) composed of a combination of the two. The patch intends to support so-called "partial" hotplug for EEH: Before we do reset, we stop and remove those PCI devices without EEH sensitive driver. The corresponding EEH devices are not detached from its PE, but with special flag. After the reset is done, those EEH devices with the special flag will be scanned one by one. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/pci: Partial tree hotplug supportGavin Shan2013-07-243-21/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When EEH error happens to one specific PE, the device drivers of its attached EEH devices (PCI devices) are checked to see the further action: reset with complete hotplug, or reset without hotplug. However, that's not enough for those PCI devices whose drivers can't support EEH, or those PCI devices without driver. So we need do so-called "partial hotplug" on basis of PCI devices. In the situation, part of PCI devices of the specific PE are unplugged and plugged again after PE reset. The patch changes pcibios_add_pci_devices() so that it can support full hotplug and so-called "partial" hotplug based on device-tree or real hardware. It's notable that pci_of_scan.c has been changed for a bit in order to support the "partial" hotplug based on dev-tree. Most of the generic code already supports that, we just need to plumb it properly on our side. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/eeh: Use safe list traversal when walking EEH devicesGavin Shan2013-07-243-9/+9
| | | | | | | | | | | | | | | | | | | | Currently, we're trasversing the EEH devices list using list_for_each_entry(). That's not safe enough because the EEH devices might be removed from its parent PE while doing iteration. The patch replaces that with list_for_each_entry_safe(). Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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