| Commit message (Collapse) | Author | Age | Files | Lines |
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The original memory map for the sbc8548 had the 64MB SODIMM flash
device misaligned by 8MB to allow a window of address space for
the soldered on 8MB device -- i.e.
start end CS<n> width Desc.
----------------------------------------------------------
fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB)
ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
However, if we want to change the configuration so that it boots
off the 64MB flash, it is in turn then aligned with a 64MB boundary,
starting at fc00_0000 (and the 8MB @ fb80_0000 -> fbff_ffff).
This makes for complicated updates, since what is the beginning
of the physical device is 8MB into its address space in the default
configuration shown above.
This issue was fixed as of u-boot commit 3fd673cf363bc86ed42eff713d4
("sbc8548: relocate 64MB user flash to sane boundary") -- in which
the SODIMM was mapped to ec00_0000 (natively aligned under efff_ffff)
and so when JP12/SW2.8 are switched, it will be a a simple 0xec --> 0xfc
mapping between the two instances.
Here we make the associated changes in the localbus flash memory
map in the dts file: indicating the 64MB device starts at ec00_0000
and that the tail end of the 64MB device (last 2 sectors) can contain
a bootloader image.
The partitions for both flash devices get a clean-up; there were
non-meaningful assignments in there that probably originated from
the MPC8548CDS on which the file was based on. Now there is just
the categorization of free space and bootloader images.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Updates to u-boot allow this board to boot off of either
the 8MB soldered on flash, or the 64MB SODIMM flash.
This is achieved by changing JP12 and SW2.8 which in turn
swaps which flash device appears on /CS0 and /CS6 respectively.
Since the flash devices are not the same size, this also
changes the MTD memory map layout on the local bus.
Here we split the common chunks out into a pre and post
include, so they can be reused by an upcoming "alternative
boot" dts file; leaving only the local bus chunk behind.
No content changes are made at this point - it is just purely
the move to using include files.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The Freescale serial port's are pretty much a 16550, however there are
some FSL specific bugs and features. Add a "fsl,ns16550" compatiable
string to allow code to handle those FSL specific issues.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The PCI-e addressing was originally patterned of the MPC8548CDS
which has PCI1, PCI2, and PCI-e. Since this board only has
PCI1 and PCI-e, it makes more sense to be similar to the MPC8568MDS
board. This does that by cutting the PCI/PCI-e I/O sizes from
16MB to 8MB and pulling the PCI-e I/O range back to 0xe280_0000
(the hole where PCI2 I/O would have been).
This also fixes a typo where an extra zero made an 8MB range a 128MB
range, removes the hole left by PCI2 from the aliases, and sets the
clocks to match the oscillators that are actually on the board.
With accompanying u-boot updates, PCI-e has been validated with
both a sky2 card (1148:9e00) and an e1000 card (8086:108b).
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Between the addition of the ecm/mcm law nodes and the fact that the
get_immrbase() has been using the range property of the SoC to determine
the base address of CCSR space we no longer need the reg property at
the soc node level. It has been ill specified and varied between device
trees to cover either the {e,m}cm-law node, some odd subset of CCSR
space or all of CCSR space.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The cell-index property isn't used on PCI nodes and is ill defined.
Remove it for now and if someone comes up with a good reason and
consistent definition for it we can add it back
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Older devices tree's used "fsl,85.." instead of the preferred
"fsl,mpc85.." for the memory controller & l2 cache controller nodes.
The EDAC code is the only use of these and has been updated for some
time to support both "fsl,85.." and "fsl,mpc85.."
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Currently it doesn't matter where the mdio nodes are placed, but with
power management support (i.e. when sleep = <> properties will take
effect), mdio nodes placement will become important: mdio controller
is a part of the ethernet block, so the mdio nodes should be placed
correctly. Otherwise we may wrongly assume that MDIO controllers are
available during sleep.
Suggested-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Does the same for the accompanying MDIO driver, and then modifies the TBI
configuration method. The old way used fields in einfo, which no longer
exists. The new way is to create an MDIO device-tree node for each instance
of gianfar, and create a tbi-handle property to associate ethernet controllers
with the TBI PHYs they are connected to.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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delete obsolete device-type property, delete model property
(use compatible property instead), prepend "fsl," to Freescale
specific properties. Add nodes to device trees that are missing them,
and fix broken property values in other trees.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Added DMA nodes for the elo/elo-plus DMA engines.
Renamed the interrupt controller alias in mpc832x_rdb.dts to ipic so that
its the same as all the other boards.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Added next-level-cache to the L1 and a reference to the new L2 label.
This is per the ePAPR 0.94 spec. Since we are't really dependent on this
today we aren't supporting the "legacy" l2-cache phandle that is specified
in the PPC v2.1 OF Binding spec.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Removed clock-frequency, big-endian, and built-in props as they aren't
specified anywhere. Also added compatible = "chrp,open-pic" in the
places it was missing.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The following adds local bus, flash and MTD partition nodes for
sbc8548. As well, a compatible field for the soc node, so that
of_platform_bus_probe() will pick it up.
Something that is provided through this newly added epld node
is the Hardware Revision which is now being utilized.
Signed-off-by: Jeremy McNicoll <jeremy.mcnicoll@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The following patch allows interrupts to occur on the
sbc8548. Currently PCI and PCI-X devices get assigned an IRQ
but the interrupt count never increases. This solves the
problem and adds PCI support as well.
Signed-off-by: Jeremy McNicoll <jeremy.mcnicoll@windriver.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This adds a v1 device tree source for the Wind River SBC8548 board.
The biggest difference between this and the MPC8548CDS reference
platform is the absence of the CDS's Arcadia peripherals and physical
access to the PCI#2 bus.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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