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There is intermittent cache coherency issue caught in toolchian tests.
Revert to use flushd.
Signed-off-by: Ley Foon Tan <lftan@altera.com>
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- flush dcache before flush instruction cache
- remork update_mmu_cache and flush_dcache_page
- add shmparam.h
Signed-off-by: Ley Foon Tan <lftan@altera.com>
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Remove the end address checking for initda function. We need to invalidate
each address line for initda instruction, from start to end address.
Signed-off-by: Ley Foon Tan <lftan@altera.com>
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Remove the end address checking for flushda function. We need to flush
each address line for flushda instruction, from start to end address.
This is because flushda instruction only flush the cache if tag and line
fields are matched.
Change to use ldwio instruction (bypass cache) to load the instruction
that causing trap. Our interest is the actual instruction that executed
by the processor, this should be uncached.
Note, EA address might be an userspace cached address.
Signed-off-by: Ley Foon Tan <lftan@altera.com>
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This patch adds functionality required for cache maintenance.
Signed-off-by: Ley Foon Tan <lftan@altera.com>
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